@Vengineerの戯言 : Twitter SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

はじめに

先週の金曜日に見つけた、Googleの「CFU Playground」

Googleがなんだかまた面白そうなものを出した
「CFU Playground」
FPGA-based "soft" processor
Currently, the only supported target is the Arty 35T board from Digilent.
The only supported host OS is Linux (Debian / Ubuntu).https://t.co/u1bjPEh4nk https://t.co/gxrd8iVcWc
— Vengineer＠ (@Vengineer) 2021年6月4日

なんか面白そうだったので、やってみました。

環境構築

Windows 10 の WSL2 (Ubuntu 20.04) で、README.md にあるように環境構築してみました。

$ git clone https://github.com/google/CFU-Playground.git
$ cd CPU-Playground.git
$ python3 -m venv venv
$ scripts/setup
....
Error: RISCV GCC toolchain not found. Please install one, following the instructions at
https://cfu-playground.readthedocs.io/en/latest/setup-guide.html#step-3-install-riscv-toolchain
Please install vivado

どうやら、RISCV GCC が必要です。ここのドキュメントに従って、

$ cd /usr/local/riscv64
$ sudo chown o+w .
$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14.tar.gz
$ tar xvfz riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14.tar.gz

.bashrc に、

export RISCV_DIR=/usr/local/riscv64/riscv64-unknown-elf-gcc-8.3.0-2020.04.1-x86_64-linux-ubuntu14/bin
export PATH=${RISCV_DIR}:${PATH}

を追加し、再実行

$ source ~/.bashrc
$ scripts/setup
....
Please install vivado

RISCV GCC のエラーが無くなりました。vivado はインストールしていないのでここまで。

例題の実行

FPGA Board の Arty ではなく、Verilator で動けばいいので、

$ proj/proj_template
$ make PLATFORM=sim load

json-c/json.h: No such file と言われたので、Google君に聞いて、下記のパッケージをインストール後、再実行。

$ sudo apt-get install libjson-c-dev
$ make PLATFORM=sim load

うーん、存在しないファイル(wrapVexRiscv_FullCfuDebug.v) を使っているっぽい。。。。

make[3]: Leaving directory '/mnt/c/Users/haray/home/verilator/CFU-Playground/soc/build/sim.proj_template/gateware/modules'
%Error: Cannot find file containing module: /mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v
%Error: This may be because there's no search path specified with -I<dir>.
        ... Looked in:
             /mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v
             /mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v.v
             /mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v.sv
             obj_dir//mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v
             obj_dir//mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v.v
             obj_dir//mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v.sv
%Error: Exiting due to 2 error(s)
make[2]: *** [/mnt/c/Users/haray/home/verilator/CFU-Playground/third_party/python/litex/litex/build/sim/core/Makefile:37: sim] Error 1
make[2]: Leaving directory '/mnt/c/Users/haray/home/verilator/CFU-Playground/soc/build/sim.proj_template/gateware'
make[1]: *** [/mnt/c/Users/haray/home/verilator/CFU-Playground/soc/sim.mk:56: run] Error 1
make[1]: Leaving directory '/mnt/c/Users/haray/home/verilator/CFU-Playground/soc'
make: *** [../proj.mk:224: load] Error 2

とりあえず、下記のようにしてファイルをコピーして、再度実行したら、Prompt らしきものが出てきた。

$ pushd third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog
$ cp -p VexRiscv_FullCfuDebug.v wrapVexRiscv_FullCfuDebug.v
$ popd
$ make PLATFORM=sim load
....
make[2]: Leaving directory '/mnt/c/Users/haray/home/verilator/CFU-Playground/soc/build/sim.proj_template/gateware'

[xgmii_ethernet] loaded (0x555ec977fef0)
[spdeeprom] loaded (addr = 0x0)
[serial2tcp] loaded (0x555ec977fef0)
[serial2console] loaded (0x555ec977fef0)
[ethernet] loaded (0x555ec977fef0)
[clocker] loaded
[clocker] sys_clk: freq_hz=1000000, phase_deg=0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jun  6 2021 11:50:27
 BIOS CRC passed (1005428a)

 Migen git sha1: 3ffd64c
 LiteX git sha1: d3560e57

--=============== SoC ==================--
CPU:            VexRiscv_FullDebug @ 1MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128KiB
SRAM:           8KiB
MAIN-RAM:       32768KiB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Executing booted program at 0x40000000

--============= Liftoff! ===============--
Hello, World!
initTfLite()

CFU Playground
==============
 1: TfLM Models menu
 2: Functional CFU Tests
 3: Project menu
 4: Performance Counter Tests
 5: TFLite Unit Tests
 6: Benchmarks
 t: trace (only works in simulation)
 Q: Exit (only works in simulation)
main>

Hello, World!の後に、initTfLite() が実行されているので、何か、できたっぽい。とりあえず、: TFLite Unit Tests の 5 を選択してみた。

main>５

Running TFLite Unit Tests

CONV TEST:
Testing SimpleTestFloat
Testing InputAndFilterSameWidthHeight
Testing SimpleTestQuantized
Testing InputOutputDifferentTypeIsError
/mnt/c/Users/haray/home/verilator/CFU-Playground/proj/proj_template/build/src/tensorflow/lite/micro/kernels/conv.cc:302 input->type != output->type (1 != 9)
Testing HybridModeIsError
/mnt/c/Users/haray/home/verilator/CFU-Playground/proj/proj_template/build/src/tensorflow/lite/micro/kernels/conv.cc Hybrid models are not supported on TFLite Micro.
Testing SimpleTestDilatedQuantized
Testing SimpleTestQuantizedPerChannel
Testing SimpleTestDilatedQuantizedPerChannel
Testing SimpleTestQuantizedPerChannelRelu6
Testing Kernel1x1QuantizedPerChannel
Testing Kernel1x1QuantizedPerChannelRelu6
Testing BroadcastPerLayerQuantizationToPerChannelShouldMatchGolden
Testing FilterDimsNotMatchingAffineQuantization
/mnt/c/Users/haray/home/verilator/CFU-Playground/proj/proj_template/build/src/tensorflow/lite/micro/kernels/conv.cc:167 affine_quantization->scale->size == 1 || affine_quantization->scale- was not true.
/mnt/c/Users/haray/home/verilator/CFU-Playground/proj/proj_template/build/src/tensorflow/lite/micro/kernels/conv.cc:167 affine_quantization->scale->size == 1 || affine_quantization->scale- was not true.
Testing Int8Input32x1Filter32x32ShouldMatchGolden
14/14 tests passed
~~~ALL TESTS PASSED~~~

DEPTHWISE_CONV TEST:
Testing SimpleTest
Testing SimpleTestQuantized
Testing SimpleTestDilatedQuantized
Testing SimpleTestRelu
Testing SimpleTestReluQuantized
Testing SimpleTestQuantizedOptimizedFilterWidth
Testing SimpleTestQuantizedPerChannel
Testing SimpleTestQuantizedPerChannelDepthMultiplier1
Testing TestQuantizedPerChannelDepthMultiplier1Relu6
Testing SimpleTestDilatedQuantizedPerChannel
Testing TestQuantizedPerChannelCompareWithFloat
Testing PerChannelBroadcastQuantizationParams
Testing FilterDimsNotMatchingAffineQuantization
/mnt/c/Users/haray/home/verilator/CFU-Playground/proj/proj_template/build/src/tensorflow/lite/micro/kernels/depthwise_conv.cc:152 affine_quantization->scale->size == 1 || affine_quantization->s was not true.
/mnt/c/Users/haray/home/verilator/CFU-Playground/proj/proj_template/build/src/tensorflow/lite/micro/kernels/depthwise_conv.cc:154 affine_quantization->scale->size != affine_quantization->zero_point->size (4 != 2)
Testing Int8Input32x4Filter32x4ShouldMatchGolden
14/14 tests passed
~~~ALL TESTS PASSED~~~

CONV TEST と DEPTHWISE_CONV TEST ができたっぽい。次は、6 の Benchmark をl を実行。

main> 6

Running Benchmarks

Benchmarks Menu
===============
 l: sequential loads benchmark (expect one miss per cache line, one every eight accesses)
 c: cached loads benchmark (expect all hits)
 8: strided loads benchmark (expect all misses)
 s: sequential stores benchmark
 i: load-increment-store benchmark (expect misses)
 x: eXit to previous menu
benchmark> l

Running sequential loads benchmark (expect one miss per cache line, one every eight accesses)
Hello, Load!

Val:835216940  Cycles: 8899280   Cycles/load: 8

おわりに

とりあえず、サンプルコードは実行できたんですが、 wrapVexRiscv_FullCfuDebug.v はどうなっているんだろうか？

soc/sim.py の 96行目の下記の部分をコメントアウトしたら、エラーが無くなった。

        soc.platform.add_source(f"{vexriscv}/verilog/wrapVexRiscv_{var}.v")

soc/sim.py は、soc/sim.mk の中で次のように使われている

SIM_RUN:=   MAKEFLAGS=-j8 $(PYRUN) ./sim.py $(LITEX_ARGS)

今回は、ここまで。

Vengineerの戯言

人生は短いけど、長いです。人生を楽しみましょう！

GoogleのCFU Playgroundをやってみた

はじめに

環境構築

例題の実行

おわりに