前回の「GoogleのCFU Playgroundをやってみた」の中の prompt に出ていたのは、LiteX なるようです。この LiteX に関して調べてみました。
2020.5.5のLiteX: an open-source SoC builder and library based on Migen Python DSLの Abstract を引用します。
LiteX is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softcores CPUs and essential peripherals, with no dependencies on proprietary IP blocks or generators. This paper provides an overview of LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries and integration capabilities. The first one is based on RISC-V core, while the second is based on a LM32 core. In the second use case, we further demonstrate the use of a fully open-source toolchain coupled with LiteX.
LiteX のスライド：LiteX: SoC builder and library
M-Labs の Migen サイト
Migen, a fully open-source Python-based toolbox, contains a HDL, a library of cores, a simulator and a build system. Migen originated from Milkymist project and stands for “Milkymist generator”.
Migen : ドキュメント
- Migen FHDL (Fragmented Hardware Description Language) allows to describe and simulate RTL circuits.
- FHDL does not follow the event-driven paradigm of most HDLs, and instead replaces it with notions of synchronous and combinatorial statements.
- While Migen offers the generation of digital logic with Python, MiSoC provides the SoC interconnect infrastructure and cores
Since 2015, LiteX has been evolving as a fork of MiSoC to provide more coherence for Enjoy-Digital’s commercial projects and to ease collaboration with other open-source communities.
ここまでで、Migen => MiSoC => LiteX 。。。