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OpenLaneを覗いてみた(その3)

はじめに

昨日の続きで、OpenLaneを眺めていきます。今回は論理合成についてです。

論理合成について

論文

論文 : OpenLANE: The Open-Source Digital ASIC Implementation Flow を読んでみて気になったのが、論理合成の部分。

論理合成に関してはいろいろなパラメータを与える必要があるんだけど、どんな感じで論理合成しているのかが論文の以下の部分から読み取れます。

Currently there are four default synthesis strategies generating four different points in the design space; those represent different degrees of area-delay trade-offs as well. A user can also add their own custom synthesis script/strategy if desired. STA is performed on each point in the design space and the result would be represented graphically on an HTML dashboard.

ドキュメント

ドキュメントでは、Synthesis に以下のように書いてあります。説明のために引用します。

The first decision in synthesis is determining the optimal synthesis strategy ::env(SYNTH_STRATEGY) for your design. For that purpose there is a flag in the flow.tcl script, -synth_explore that runs a synthesis strategy exploration and reports the results in a table under <run_path>/reports/.

Then you need to consider the best values for the SYNTH_MAX_FANOUT.

If your macro is huge (200k+ cells), then you might want to try setting SYNTH_NO_FLAT to 1, which will postpone the flattening of the design during synthesis until the very end.

Other configurations like SYNTH_SIZING, SYNTH_BUFFERING, and other synthesis configurations don't have to be changed. However, the advanced user can check this documentation for more details about those configurations and their values.

つまり、flow.tcl スクリプトの env(SYNTH_STRATEGY) にて設定すると。そして、-synth_explore にて論理合成時にこの値を使うと。結果は、<run_path>/reports に出てくると。

また、configuration というディレクトリには、各変数の説明があり、その中にも SYNTH_STRATEGY の説明もあります。

どうやら、この SYNTH_STRATEGY は、DELAY を 0 - 3 と AREA を 0 - 2 に設定できるようで、デフォルト値は (AREA 0) 。

Strategies for abc logic synthesis and technology mapping
Possible values are DELAY/AREA 0-3/0-2; the first part refers to the optimization target of the synthesis strategy (area vs. delay) and the second one is an index.
(Default: AREA 0)
``

[synthesis.tcl](https://github.com/The-OpenROAD-Project/OpenLane/blob/master/configuration/synthesis.tcl) というファイルにて、デフォルト値に設定しています。

set ::env(SYNTH_BIN) yosys set ::env(SYNTH_SCRIPT) $::env(SCRIPTS_DIR)/yosys/synth.tcl set ::env(SYNTH_NO_FLAT) 0 set ::env(SYNTH_CLOCK_UNCERTAINITY) 0.25 set ::env(SYNTH_CLOCK_TRANSITION) 0.15 set ::env(SYNTH_TIMING_DERATE) 0.05 set ::env(SYNTH_SHARE_RESOURCES) 1 set ::env(SYNTH_BUFFERING) 1 set ::env(SYNTH_SIZING) 0 set ::env(SYNTH_MAX_FANOUT) 5 set ::env(SYNTH_STRATEGY) "AREA 0" set ::env(SYNTH_ADDER_TYPE) "YOSYS" set ::env(CLOCK_BUFFER_FANOUT) 16 set ::env(SYNTH_READ_BLACKBOX_LIB) 0 set ::env(SYNTH_TOP_LEVEL) 0 set ::env(SYNTH_FLAT_TOP) 0 set ::env(IO_PCT) 0.2

set ::env(BASE_SDC_FILE) $::env(OPENLANE_ROOT)/scripts/base.sdc

# SYNTH_STRATEGY を変えてみる

昨日の spm デザインの結果を見てみたら、下記のように SYNTHE_STRATEGY には (AREA 0) が設定されていた。これはデフォルト値ですね。

grep -r SYNTH_STRATEGY designs/spm/runs/* designs/spm/runs/openlane_test/config.tcl:set ::env(SYNTH_STRATEGY) {AREA 0} designs/spm/runs/openlane_test/config.tcl:set ::env(SYNTH_STRATEGY) {AREA 0}

config.tcl に、SYNTH_STRATEGY を追加してみたら、

Design

set ::env(DESIGN_NAME) "spm"

set ::env(VERILOG_FILES) [glob ./designs/spm/src/*.v]

set ::env(CLOCK_PERIOD) "10.000" set ::env(CLOCK_PORT) "clk" set ::env(CELL_PAD) 4 set ::env(SYNTH_STRATEGY) "AREA 1"

set ::env(FP_PIN_ORDER_CFG) $::env(OPENLANE_ROOT)/designs/spm/pin_order.cfg

set filename ./designs/$::env(DESIGN_NAME)/$::env(PDK)$::env(STD_CELL_LIBRARY)config.tcl if { [file exists $filename] == 1} { source $filename }





make test
....



grep -r SYNTH_STRATEGY designs/spm/runs*
designs/spm/run_delay/openlane_test/config.tcl:set ::env(SYNTH_STRATEGY) {DELAY 1}
designs/spm/run_delay/openlane_test/config.tcl:set ::env(SYNTH_STRATEGY) {DELAY 1}



SYNTHE_STRATEGY には (DELAY 1) が設定されるようになりました。

# 結果の比較

AREA 0 の時の結果




otal 68
-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 13:45 1-synthesis.chk.rpt.strategy4
-rwxrwxrwx 1 vengineer vengineer   710 Dec 18 13:45 1-synthesis.stat.rpt.strategy4
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 13:45 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 13:45 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 13:47 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 13:47 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 22352 Dec 18 13:47 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 20417 Dec 18 13:47 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 13:47 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4809 Dec 18 13:47 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer   452 Dec 18 13:47 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 13:47 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 13:47 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 13:47 2-synthesis_sta.worst_slack.rpt



AREA 1の時の結果




ls -l designs/spm/runs/openlane_test/reports/synthesis/
total 68
-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 14:00 1-synthesis.chk.rpt.strategy5
-rwxrwxrwx 1 vengineer vengineer   710 Dec 18 14:00 1-synthesis.stat.rpt.strategy5
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 14:00 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 14:00 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 14:01 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 14:01 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 22352 Dec 18 14:01 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 20417 Dec 18 14:01 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 14:01 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4809 Dec 18 14:01 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer   452 Dec 18 14:01 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:01 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:01 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 14:01 2-synthesis_sta.worst_slack.rpt



AREA 2 の時の結果




-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 14:04 1-synthesis.chk.rpt.strategy6
-rwxrwxrwx 1 vengineer vengineer   710 Dec 18 14:04 1-synthesis.stat.rpt.strategy6
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 14:04 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 14:04 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 14:05 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 14:05 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 22352 Dec 18 14:05 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 20417 Dec 18 14:05 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 14:05 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4809 Dec 18 14:05 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer   452 Dec 18 14:05 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:05 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:05 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 14:05 2-synthesis_sta.worst_slack.rpt



AREA を 0, 1, 2 に変えても結果は変わりませんでした。

DELAY 0 の時の結果




total 72
-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 14:54 1-synthesis.chk.rpt.strategy0
-rwxrwxrwx 1 vengineer vengineer   827 Dec 18 14:54 1-synthesis.stat.rpt.strategy0
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 14:54 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 14:54 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 14:54 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 14:54 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 19322 Dec 18 14:54 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 18438 Dec 18 14:54 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 14:54 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4203 Dec 18 14:54 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer  5478 Dec 18 14:54 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:54 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:54 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 14:54 2-synthesis_sta.worst_slack.rpt



DELAY 1の時の結果




ls -l designs/spm/runs/openlane_test/reports/synthesis/
total 72
-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 13:39 1-synthesis.chk.rpt.strategy1
-rwxrwxrwx 1 vengineer vengineer   866 Dec 18 13:39 1-synthesis.stat.rpt.strategy1
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 13:39 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 13:39 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 13:40 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 13:40 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 19343 Dec 18 13:40 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 18438 Dec 18 13:40 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 13:40 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4198 Dec 18 13:40 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer  5478 Dec 18 13:40 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 13:40 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 13:40 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 13:40 2-synthesis_sta.worst_slack.rpt



DELAY 2の時の結果




ls -l designs/spm/runs/openlane_test/reports/synthesis/
total 72
-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 14:10 1-synthesis.chk.rpt.strategy2
-rwxrwxrwx 1 vengineer vengineer   866 Dec 18 14:10 1-synthesis.stat.rpt.strategy2
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 14:10 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 14:10 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 14:12 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 14:12 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 19343 Dec 18 14:12 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 18438 Dec 18 14:12 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 14:12 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4198 Dec 18 14:12 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer  5478 Dec 18 14:12 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:12 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:12 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 14:12 2-synthesis_sta.worst_slack.rpt



DELAY 3 の時の結果




total 72
-rwxrwxrwx 1 vengineer vengineer   161 Dec 18 14:51 1-synthesis.chk.rpt.strategy3
-rwxrwxrwx 1 vengineer vengineer   827 Dec 18 14:51 1-synthesis.stat.rpt.strategy3
-rwxrwxrwx 1 vengineer vengineer   665 Dec 18 14:51 1-synthesis_dff.stat
-rwxrwxrwx 1 vengineer vengineer   626 Dec 18 14:51 1-synthesis_pre.stat
-rwxrwxrwx 1 vengineer vengineer     8 Dec 18 14:52 2-synthesis_sta.area.rpt
-rwxrwxrwx 1 vengineer vengineer   274 Dec 18 14:52 2-synthesis_sta.clock_skew.rpt
-rwxrwxrwx 1 vengineer vengineer 19322 Dec 18 14:52 2-synthesis_sta.max.rpt
-rwxrwxrwx 1 vengineer vengineer 18438 Dec 18 14:52 2-synthesis_sta.min.rpt
-rwxrwxrwx 1 vengineer vengineer   842 Dec 18 14:52 2-synthesis_sta.power.rpt
-rwxrwxrwx 1 vengineer vengineer  4203 Dec 18 14:52 2-synthesis_sta.rpt
-rwxrwxrwx 1 vengineer vengineer  5478 Dec 18 14:52 2-synthesis_sta.slew.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:52 2-synthesis_sta.tns.rpt
-rwxrwxrwx 1 vengineer vengineer   175 Dec 18 14:52 2-synthesis_sta.wns.rpt
-rwxrwxrwx 1 vengineer vengineer   407 Dec 18 14:52 2-synthesis_sta.worst_slack.rpt



DELAY は、１と２では同じでした。０と３を指定すると、Global Routing にてエラーになりました。このデザインでは、設定してはいけないようです。
AREAとDELAYの違いは以下のファイル

ファイルのサイズが違うのは、下記の５つです。
- 1-synthesis.stat.rpt.strategyX と 1-synthesis.stat.rpt.strategyY
- 2-synthesis_sta.max.rpt
- 2-synthesis_sta.min.rpt
- 2-synthesis_sta.rpt
- 2-synthesis_sta.slew.rpt

AREA 0, 1, 2 を指定したときは、同じ




    

  1. Printing statistics.
    2. 





=== spm ===



   Number of wires:                337
   Number of wire bits:            368
   Number of public wires:          99
   Number of public wire bits:     130
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                333
     sky130_fd_sc_hda21oi_2        1
     sky130_fd_sc_hda22o_2        31
     sky130_fd_sc_hda31oi_2        1
     sky130_fd_sc_hdand2_2        31
     sky130_fd_sc_hdbuf_1        141
     sky130_fd_sc_hddfrtp_2       64
     sky130_fd_sc_hdinv_2          2
     sky130_fd_sc_hdo2bb2a_2      62



   Chip area for module '\spm': 3480.838400



DELAY 0, 3 を指定したときは、Global Routingでエラーになる。論理合成はできる。DELAY 0と3は同じ値。DELAY 1と2は同じ値。

DELAY ０を指定したとき (ただし、global routingでエラーになる）




    

  1. Printing statistics.
    2. 





=== spm ===



   Number of wires:                508
   Number of wire bits:            539
   Number of public wires:          99
   Number of public wire bits:     130
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                504
     sky130_fd_sc_hda21o_2         1
     sky130_fd_sc_hda21oi_2       31
     sky130_fd_sc_hdand2_2        32
     sky130_fd_sc_hdbuf_1          1
     sky130_fd_sc_hddfrtp_2       64
     sky130_fd_sc_hdinv_2        157
     sky130_fd_sc_hdnand2_2       93
     sky130_fd_sc_hdnand3_2        1
     sky130_fd_sc_hdnor2_2        62
     sky130_fd_sc_hdnor3_2        31
     sky130_fd_sc_hd__o21ai_2       31



   Chip area for module '\spm': 4356.678400



DELAY 1, 2 を指定したとき





    

  1. Printing statistics.
    2. 





=== spm ===



   Number of wires:                384
   Number of wire bits:            415
   Number of public wires:          99
   Number of public wire bits:     130
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                380
     sky130_fd_sc_hda21o_2         1
     sky130_fd_sc_hdand2_2        31
     sky130_fd_sc_hdand2b_2        1
     sky130_fd_sc_hdand3_2         1
     sky130_fd_sc_hdbuf_1          1
     sky130_fd_sc_hddfrtp_2       64
     sky130_fd_sc_hdinv_2         64
     sky130_fd_sc_hdnand2_2       93
     sky130_fd_sc_hdnand3b_2      31
     sky130_fd_sc_hdnor2_2        31
     sky130_fd_sc_hdo21ai_2       31
     sky130_fd_sc_hdo21bai_2      31



   Chip area for module '\spm': 3928.768000



DELAY 3を指定したとき




    

  1. Printing statistics.
    2. 





=== spm ===



   Number of wires:                384
   Number of wire bits:            415
   Number of public wires:          99
   Number of public wire bits:     130
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                380
     sky130_fd_sc_hda21o_2         1
     sky130_fd_sc_hdand2_2        31
     sky130_fd_sc_hdand2b_2        1
     sky130_fd_sc_hdand3_2         1
     sky130_fd_sc_hdbuf_1          1
     sky130_fd_sc_hddfrtp_2       64
     sky130_fd_sc_hdinv_2         64
     sky130_fd_sc_hdnand2_2       93
     sky130_fd_sc_hdnand3b_2      31
     sky130_fd_sc_hdnor2_2        31
     sky130_fd_sc_hdo21ai_2       31
     sky130_fd_sc_hdo21bai_2      31



   Chip area for module '\spm': 3928.768000



DELAY 3 を指定したとき (ただし、global routing中にエラーになる）




    

  1. Printing statistics.
    2. 





=== spm ===



   Number of wires:                508
   Number of wire bits:            539
   Number of public wires:          99
   Number of public wire bits:     130
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                504
     sky130_fd_sc_hda21o_2         1
     sky130_fd_sc_hda21oi_2       31
     sky130_fd_sc_hdand2_2        32
     sky130_fd_sc_hdbuf_1          1
     sky130_fd_sc_hddfrtp_2       64
     sky130_fd_sc_hdinv_2        157
     sky130_fd_sc_hdnand2_2       93
     sky130_fd_sc_hdnand3_2        1
     sky130_fd_sc_hdnor2_2        62
     sky130_fd_sc_hdnor3_2        31
     sky130_fd_sc_hd__o21ai_2       31



   Chip area for module '\spm': 4356.678400



# おわりに

論理合成では、SYNTH_STRATEGY を変えることで探索できるっぽい。

上記の例題では、AREAに関しては変化なし。DELAYに関しても変化なし。AREAとDELAYでは、AREAを指定した方が面積が少なくなっています。当たり前でしょうが。。。