Vengineerの戯言

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OpenLaneを覗いてみた(その4)

はじめに

今回は、"make test" のログを眺めてみます。

make test

make test
        docker run --rm -v /XXXX/OpenLane:/openlane -v /XXXXX/OpenLane/designs:/openlane/inst
all -v /XXXXX/OpenLane/pdks:/mnt/c/Users/haray/home/OpenLane/OpenLane/pdks -e PDK_ROOT=/XXXXX/
OpenLane/pdks --user 1000:1000 -e DISPLAY=:0 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/vengineer/.Xauthority:/.Xauthority --network host efabless/
openlane:2021.12.17_05.07.41 sh -c "./flow.tcl -design spm -tag openlane_test -disable_output -overwrite"
[INFO]:
         ___   ____   ___  ____   _       ____  ____     ___
        /   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
        |   | |  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
        | O | |   _/    _]|  |  || |___ |     ||  |  ||    _]
        |   | |  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
        \___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: 2021.12.17_05.07.41
[INFO]: Running non-interactively
[INFO]: Using design configuration at /openlane/designs/spm/config.tcl
[INFO]: Sourcing Configurations from /openlane/designs/spm/config.tcl
[INFO]: PDKs root directory: /mnt/c/Users/haray/home/OpenLane/OpenLane/pdks
[INFO]: PDK: sky130A
[INFO]: Setting PDKPATH to /mnt/c/Users/haray/home/OpenLane/OpenLane/pdks/sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library is set to: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /openlane/designs/spm/config.tcl
[WARNING]: Removing exisiting run /openlane/designs/spm/runs/openlane_test
[INFO]: Current run directory is /openlane/designs/spm/runs/openlane_test
[INFO]: Storing configs into config.tcl ...
[INFO]: Preparing LEF Files
[INFO]: Extracting the number of available metal layers from /mnt/c/Users/haray/home/OpenLane/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techl
ef/sky130_fd_sc_hd.tlef
[INFO]: The available metal layers (6) are li1  met1  met2  met3  met4  met5
[INFO]: Merging LEF Files...
[INFO]: Trimming Liberty...
[INFO]: Generating Exclude List...
[INFO]: Generating Exclude List...
[INFO]: Creating ::env(DONT_USE_CELLS)...
[INFO]: Preparation complete
[INFO]: Incremented step index to 0.

docker にて、"./flow.tcl -design spm -tag openlane_test -disable_output -overwrite" を実行しています。

flow.tcl の中を覗いてみると、後半の部分から実行されているようです。最初に、OPENLANEの文字が表示され、各コマンドが実行されていきます。

set flags {-interactive -it -drc -lvs -synth_explore}

parse_key_args "flow.tcl" argv arg_values $options flags_map $flags -no_consume

puts_info {
         ___   ____   ___  ____   _       ____  ____     ___
        /   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
        |   | |  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
        | O | |   _/    _]|  |  || |___ |     ||  |  ||    _]
        |   | |  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
        \___/ |__| |_____||__|__||_____||__|__||__|__||_____|

}

if {[catch {exec cat $::env(OPENLANE_ROOT)/installed_version} ::env(OPENLANE_VERSION)]} {
        if {[catch {exec git --git-dir $::env(OPENLANE_ROOT)/.git describe --tags} ::env(OPENLANE_VERSION)]} {
                # if no tags yet
                if {[catch {exec git --git-dir $::env(OPENLANE_ROOT)/.git log --pretty=format:'%h' -n 1} ::env(OPENLANE_
VERSION)]} {
                        set ::env(OPENLANE_VERSION) "N/A"
                }
        }
}

puts_info "Version: $::env(OPENLANE_VERSION)"

if [catch {exec python3 $::env(OPENLANE_ROOT)/dependencies/verify_versions.py} ::env(VCHECK_OUTPUT)] {
        puts_warn $::env(VCHECK_OUTPUT)
        puts_warn "OpenLane may not function properly."
}

if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
        puts_info "Running interactively"
        if { [info exists arg_values(-file)] } {
                run_file [file normalize $arg_values(-file)] {*}$argv
        } else {
                run_interactive_mode {*}$argv
        }
} elseif { [info exists flags_map(-drc)] } {
        run_magic_drc_batch {*}$argv
} elseif { [info exists flags_map(-lvs)] } {
        run_lvs_batch {*}$argv
} elseif { [info exists flags_map(-synth_explore)] } {
        prep {*}$argv
        run_synth_exploration
} else {
        puts_info "Running non-interactively"
        run_non_interactive_mode {*}$argv
}

下記の最後の run_non_interactive_mode {*}$argv が実行されます。

} else {
        puts_info "Running non-interactively"
        run_non_interactive_mode {*}$argv
}

run_non_interactive_mode にて、各オプションを取り出します。

proc run_non_interactive_mode {args} {
        set options {
                {-design required}
                {-from optional}
                {-to optional}
                {-save_path optional}
                {-no_lvs optional}
            {-no_drc optional}
            {-no_antennacheck optional}
            {-override_env optional}
        }
        set flags {-save}
        parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume

下記のコマンドから、-design オプションが取り出されます。

./flow.tcl -design spm -tag openlane_test -disable_output -overwrite

下記の部分で実行するコマンドを決めます。lvs, drc, antennacheck は、-no_XXXX にて実行しないように設定できます。

    set LVS_ENABLED [expr ![info exists flags_map(-no_lvs)] ]
    set DRC_ENABLED [expr ![info exists flags_map(-no_drc)] ]
    set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]

    set steps [dict create \
                "synthesis" {run_synthesis "" } \
                "floorplan" {run_floorplan ""} \
                "placement" {run_placement_step ""} \
                "cts" {run_cts_step ""} \
                "routing" {run_routing_step ""}\
                "diode_insertion" {run_diode_insertion_2_5_step ""} \
                "gds_magic" {run_magic ""} \
                "gds_drc_klayout" {run_klayout ""} \
                "gds_xor_klayout" {run_klayout_gds_xor ""} \
                "lvs" "run_lvs_step $LVS_ENABLED" \
                "drc" "run_drc_step $DRC_ENABLED" \
                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
                "cvc" {run_lef_cvc}
    ]
  • synthesis
  • floorplan
  • placement
  • cts
  • routing
  • diode_insertion
  • gds_magic
  • gds_drc_klayout
  • gds_xor_klayout
  • lvs
  • drc
  • antenna_check
  • cvc

-from と -to オプションで上記の step の最初と最後を決めることもできるようですね。

下記の部分で、steps に登録されたステップを実行することになります。

    set_if_unset arg_values(-from) $::env(CURRENT_STEP);
    set exe 0;
    dict for {step_name step_exe} $steps {
        if { [ string equal $arg_values(-from) $step_name ] } {
            set exe 1;
        }

        if { $exe } {
            # For when it fails
            set ::env(CURRENT_STEP) $step_name
            [lindex $step_exe 0] [lindex $step_exe 1] ;
        }

        if { [ string equal $arg_values(-to) $step_name ] } {
            set exe 0:
            break;
        }

    }

以降、登録されたステップで実行されていきます。### の行は追加したものです。

[INFO]: Incremented step index to 0.
[INFO]: Running Synthesis...
[INFO]: Changing netlist from 0 to /openlane/designs/spm/runs/openlane_test/results/synthesis/spm.v

### synthesis
[INFO]: Incremented step index to 1.
[INFO]: Running Static Timing Analysis...
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...

### PDN Placement
[INFO]: Incremented step index to 2.
[INFO]: Core area width: 87.86
[INFO]: Core area height: 87.04
[WARNING]: Current core area is too small for a power grid
[WARNING]: !!! THE POWER GRID WILL BE MINIMIZED. !!!
[INFO]: Final Vertical PDN Offset: 14.643333333333333
[INFO]: Final Horizontal PDN Offset: 14.506666666666668
[INFO]: Final Vertical PDN Pitch: 29.286666666666665
[INFO]: Final Horizontal PDN Pitch: 29.013333333333335
[INFO]: Changing layout from 0 to /openlane/designs/spm/runs/openlane_test/tmp/floorplan/3-initial_fp.def

### IO Placement
[INFO]: Incremented step index to 3.
[INFO]: Running IO Placement...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/floorplan/3-initial_fp.def to /openlane/designs/spm/runs/openlane_test/tmp/floorplan/4-io.def

### Tap/Decap Insertion
[INFO]: Incremented step index to 4.
[INFO]: Running Tap/Decap Insertion...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/floorplan/4-io.def to /openlane/designs/spm/runs/openlane_test/results/floorplan/spm.def
[INFO]: Power planning the following nets
[INFO]: Power: VPWR
[INFO]: Ground: VGND

### PDN Generation
[INFO]: Incremented step index to 5.
[INFO]: Generating PDN...
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/floorplan/spm.def to /openlane/designs/spm/runs/openlane_test/tmp/floorplan/6-pdn.def
[INFO]: Running Placement...

### Global Placement
[INFO]: Incremented step index to 6.
[INFO]: Running Global Placement...
[INFO]: Global placement was successful
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/floorplan/6-pdn.def to /openlane/designs/spm/runs/openlane_test/tmp/placement/7-global.def

### Resize Design Optimizations
[INFO]: Incremented step index to 7.
[INFO]: Running Resizer Design Optimizations...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/placement/7-global.def to /openlane/designs/spm/runs/openlane_test/tmp/placement/8-resizer.def

### Verilog HDL Netlist生成
[INFO]: Incremented step index to 8.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/synthesis/spm.v to /openlane/designs/spm/runs/openlane_test/results/placement/spm.resized.v

### Detailed Placement
[INFO]: Incremented step index to 9.
[INFO]: Running Detailed Placement...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/placement/8-resizer.def to /openlane/designs/spm/runs/openlane_test/results/placement/spm.def
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/placement/spm.def to /openlane/designs/spm/runs/openlane_test/results/placement/spm.def

### CTS
[INFO]: Incremented step index to 10.
[INFO]: Running TritonCTS...
[INFO]: Trimming Liberty...
[INFO]: Generating Exclude List...

### Verilog HDL Netlist生成
[INFO]: Incremented step  index to 11.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/placement/spm.resized.v to /openlane/designs/spm/runs/openlane_test/results/cts/spm.v

### Resizer Timing Optimizations
[INFO]: Incremented step index to 12.
[INFO]: Running Resizer Timing Optimizations...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/cts/spm.def to /openlane/designs/spm/runs/openlane_test/tmp/cts/13-resizer_timing.def

### Verilog HDL Netlist 生成
[INFO]: Incremented step index to 13.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/cts/spm.v to /openlane/designs/spm/runs/openlane_test/results/cts/spm.resized.v
[INFO]: Routing...

### Resizer Timing Optimizations
[INFO]: Incremented step index to 14.
[INFO]: Running Resizer Timing Optimizations...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/cts/13-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def

### Verilog HDL Netlist 生成
[INFO]: Incremented step index to 15.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/cts/spm.resized.v to /openlane/designs/spm/runs/openlane_test/results/routing/spm.resized.v

### Detailed Placement
[INFO]: Incremented step index to 16.
[INFO]: Running Detailed Placement...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def

### Global Routing
[INFO]: Incremented step index to 17.
[INFO]: Running Global Routing...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def
[INFO]: Changing layout from 0 to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide
[INFO]: Current Def is /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def
[INFO]: Current Guide is /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide

### Fill Insertion
[INFO]: Incremented step index to 18.
[INFO]: Running Fill Insertion...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/19-fill.def

### Verilog HDL Netlist 生成
[INFO]: Incremented step index to 19.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/routing/spm.resized.v to /openlane/designs/spm/runs/openlane_test/tmp/routing/19-global.v

### Detailed Routing
[INFO]: Incremented step index to 20.
[INFO]: Running Detailed Routing...
[INFO]: No DRC violations after detailed routing.
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/19-fill.def to /openlane/designs/spm/runs/openlane_test/results/routing/spm.def

### Verilog HDL Netlist 生成
[INFO]: Incremented step index to 21.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/tmp/routing/19-global.v to /openlane/designs/spm/runs/openlane_test/tmp/routing/21-detailed.v

### SPEF Extraction x 3
[INFO]: Incremented step index to 22.
[INFO]: Running SPEF Extraction...
[INFO]: Incremented step index to 23.
[INFO]: Running SPEF Extraction...
[INFO]: Incremented step index to 24.
[INFO]: Running SPEF Extraction...

### Static Timing Analysis x 2
[INFO]: Incremented step index to 25.
[INFO]: Running Static Timing Analysis...
[INFO]: Incremented step index to 26.
[INFO]: Running Static Timing Analysis...

### GDSII 生成
[INFO]: Incremented step index to 27.
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDS II...
[INFO]: Running Klayout to re-generate GDS-II...
[INFO]: Streaming out GDS II...
[INFO]: Running Klayout to re-generate GDS-II...

### GDSII 生成
[INFO]: Incremented step index to 28.
[INFO]: Streaming out GDS II...
[INFO]: Back-up GDS-II streamed out.

### XOR Klayout
[INFO]: Incremented step index to 29.
[INFO]: Running XOR on the layouts using Klayout...
[WARNING]: /openlane/designs/spm/runs/openlane_test/results/finishing/spm.klayout.gds wasn't found. Skipping GDS XOR.

### Magic Spice
[INFO]: Incremented step index to 30.
[INFO]: Running Magic Spice Export from LEF...
[INFO]: No illegal overlaps detected during extraction.

### Powering Verilog HDL Netlist 生成
[INFO]: Incremented step index to 31.
[INFO]: Writing Powered Verilog...

### Verilog HDL Netlist 生成
[INFO]: Incremented step index to 32.
[INFO]: Writing Verilog...
[INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is.
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/tmp/routing/21-detailed.v to /openlane/designs/spm/runs/openlane_test/tmp/finishing/31-powered_netlist.v

### LEF VLS
[INFO]: Incremented step index to 33.
[INFO]: Running LEF LVS...
[INFO]: /openlane/designs/spm/runs/openlane_test/results/finishing/spm.spice against /openlane/designs/spm/runs/openlane_test/tmp/finishing/31-powered_netlist.v
[INFO]: No LVS mismatches.

### DRC
[INFO]: Incremented step index to 34.
[INFO]: Running Magic DRC...
[INFO]: Converting Magic DRC Violations to Magic Readable Format...
[INFO]: Converting Magic DRC Violations to Klayout XML Database...
[INFO]: Converting DRC Violations to RDB Format...
[INFO]: Converted DRC Violations to RDB Format
[INFO]: No DRC violations after GDS streaming out.
[INFO]: Running Antenna Checks...

### OpenROAD Antenna Rule Checker
[INFO]: Incremented step index to 35.
[INFO]: Running OpenROAD Antenna Rule Checker...

### CVC
[INFO]: Incremented step index to 36.
[INFO]: Running CVC
[INFO]: Saving Magic Views in /openlane/designs/spm/runs/openlane_test/results/final
[INFO]: Calculating Runtime From the Start...
[INFO]: Saving runtime environment...
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: spm
Run Directory: /openlane/designs/spm/runs/openlane_test
----------------------------------------

Magic DRC Summary:
Source: /openlane/designs/spm/runs/openlane_test/reports/finishing/drc.rpt
Total Magic DRC violations is 0
----------------------------------------

LVS Summary:
Source: /openlane/designs/spm/runs/openlane_test/logs/finishing/34-spm.lvs.lef.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
----------------------------------------

Antenna Summary:
Source: /openlane/designs/spm/runs/openlane_test/reports/finishing/antenna.rpt
Number of pins violated: 0
Number of nets violated: 0
[INFO]: check full report here: /openlane/designs/spm/runs/openlane_test/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
Basic test passed

上記のログから生成されたファイルです。各ステップで生成されたファイルを眺めてみると、いろいろと分かりそうです。

### synthesis (results/synthesis/spm.v)
### PDN Placement (tmp/floorplan/3-initial_fp.def)
### IO Placement (tmp/floorplan/3-initial_fp.def => tmp/floorplan/4-io.def)
### Tap/Decap Insertion (tmpl/floorpaln/4-io.def => results/floorplan/spm.def)
### PDN Generation (tmp/foorplan/6-pdn.def)
### Global Placement (tmp/floorplan/6-pdn.def => tmp/placement/7-global.def)
### Resize Design Optimizations (tmp/placement/7-global.def => tmp/placement/8-resizer.def)
### Verilog HDL Netlist生成 (results/synthesis/spm.v => results/placement/spm.resizer.v)
### Detailed Placement (tmp/placement/8-resizer.def => results/placement/spm.def)
### CTS
### Verilog HDL Netlist生成 (results//placement/spm.resized.v => results/cts/spm.v)
### Resizer Timing Optimizations (results/cts/spm.def => tmp/cts/13-resizer_timing.def)
### Verilog HDL Netlist生成 (results/cts/spm.v => results/cts/spm.resized.v)
### Resizer Timing Optimizations (tmp/cts/13-resizer_timing.def => tmp/routing/15-resizer_timing.def)
### Verilog HDL Netlist生成 (results/cts/spm.resized.v => results/routing/spm.resized.v)
### Detailed Placement (tmp/routing/15_resizer_timing.def => tmp/routing/15-resizer_timing.def)
### Global Routing tmp/routing/15-resizer_timingg.def => tmp/routing/18-global.def, tmp/routing/18-globa.guide)
### Fill Insertion (tmp/routing/18-global.def => tmp/routing/19-fill.def)
### Verilog HDL Netlist 生成 (results/routing/spm.resized.v => tmp/routing/19-global.v)
### Detailed Routing (tmp/ruting/19-fill.def => results/routing/spm.def)
### Verilog HDL Netlist 生成 (tmp/routing/19-global.v => tmp/routing/21-detailed.v)
### SPEF Extraction x 3
### Static Timing Analysis x 2
### GDSII 生成
### GDSII 生成
### XOR Klayout (spm.klayout.gds)
### Magic Spice
### Powering Verilog HDL Netlist 生成
### Verilog HDL Netlist 生成 (tmp/finishing/31-powered_netlist.v)
### LEF VLS
### DRC
### OpenROAD Antenna Rule Checker
### CVC
Magic DRC Summary: (drc.rpt)
LVS Summary:(34-spm.lvs.lef.log)
Antenna Summary:(antenna.rpt)
(report/final_summary_report.csv)

おわりに

今回は、OpenLaneのログを見てみました。