はじめに

Xilinx Vitis の中を調べるのその６．

今回からは、C/RTL cosimulation にて、Random Stall オプションを ON にした時に生成されるファイルをみていきます。

Random Stall

C/RTL Cosimulation 時に、Random Stall をイネーブルにすると生成されるコードが変わります。どんなふうに変わったかをみていきます。

Random Stall では、UVM(Universal Verification Methodology) を使っています。Xilinx xsim では、このために UVM を導入しているっぽいです。

UVMについては、このブログでもかなりの量書いていますので、参考にしてくださいね。

vengineer.hatenablog.com

生成されるファイルは？

sim ディレクトリの下に下記のようなファイル/ディレクトリが生成されます。

autowrap
multi_apuint_cosim_random_stall.json
report
tv
verilog
wrapc
wrapc_pc

1つだけ、multi_apuint_cosim_random_stall.json というファイルが生成されています。

このファイルの中で Random Stall の条件等が書かれているようです。multi_in0/multi_in1/ap_stat の delay の部分が Random Stall の条件で、遅延を 0, 1, 2に振って、0 が 80%、1 と 0 が 10%毎という感じですかね。

{
    "__comment__syntax_for_stall_constraint" : "C argument name for ap_hs/ap_fifo/axis; ap_start; ap_continue; bundle name plus wr/rd or bundle name plus channel
type for maxi/axilite port: constraint code",
    "__comment__block_ctrl_stall" : "ap_start/ap_continue stall means when ap_ready/ap_done is asserted, TB will wait a stall time to assert next ap_start/ap_cont
inue.",
    "__comment__axi_trans_stall" : "bundle name plus wr/rd is to define one axi transfer stall. wr is for write transfer. rd is for read transfer",
    "__comment__channel_stall" : "bundle name plus channel type is to define stall on each channel. channel types are wctrl, wdata, wbrsp, rctrl, rdata.",
    "__comment__constraint_code" : "constraint code must follow system verilog contraint syntax. Brace letter should be included. The constraint variable is delay
.",
    "__comment__stall_constraint_example" : "port_stall_constraint is the constraint code used in default random stall test.",
    "port_stall_constraint" : {
        "multi_in0"    : "{
                                delay dist {0:=8, 1:=1, 2:=1, [0:2]:/2};
                                delay inside {[0:2]};
                                }" ,
        "multi_in1"    : "{
                                delay dist {0:=8, 1:=1, 2:=1, [0:2]:/2};
                                delay inside {[0:2]};
                                }" ,
        "multi_out"    : "{
                                delay dist {0:=8, 1:=1, 2:=1, [0:2]:/2};
                                delay inside {[0:2]};
                                }" ,
        "ap_start"    : "{
                                delay dist {0:=8, 1:=1, 2:=1, [0:2]:/2};
                                delay inside {[0:2]};
                                }" ,
    }
}

autowrap、tv、wrapc、wrapc_pc ディレクトリの中は、Random Stall が OFF の時と同じっぽいです。

以下、違う部分をみていきます。

report

report ディレクトリは、ログファイル用のようです。

multi_apuint_cosim.rpt
verilog

multi_apuint_cosim.rptの内容は下記のようになっています。Latency/Internalのクロックサイクルの統計値のようです。

Report time       : Sun 26 Jun 2022 03:49:00 PM JST.
Solution          : solution1.
Simulation tool   : xsim.

+----------+----------+-----------------------------------------------+-----------------------------------------------+----------------------+
|          |          |             Latency(Clock Cycles)             |              Interval(Clock Cycles)           | Total Execution Time |
+   RTL    +  Status  +-----------------------------------------------+-----------------------------------------------+    (Clock Cycles)    +
|          |          |      min      |      avg      |      max      |      min      |      avg      |      max      |                      |
+----------+----------+-----------------------------------------------+-----------------------------------------------+----------------------+
|      VHDL|        NA|             NA|             NA|             NA|             NA|             NA|             NA|                    NA|
|   Verilog|      Pass|              2|              3|              4|              1|              1|              5|                    20|
+----------+----------+-----------------------------------------------+-----------------------------------------------+----------------------+

verilog ディレクトリには、以下の3つのファイルが生成されました。

lat.rpt
multi_apuint.log
result.transaction.rpt

lat.rpt は、上記のmulti_apuint_cosim.rptを生成するためのデータっぽいです。

$MAX_LATENCY = "4"
$MIN_LATENCY = "2"
$AVER_LATENCY = "3"
$MAX_THROUGHPUT = "5"
$MIN_THROUGHPUT = "1"
$AVER_THROUGHPUT = "1"
$TOTAL_EXECUTE_TIME = "20"

multi_apuint.logは、シミュレーションのログファイルです。前半で C++のコードに対するシミュレーションを実行しています。xsim コマンドの引数の-testplusarg UVM_VERBOSITY=UVM_LOW -testplusarg UVM_TESTNAME=multi_apuint_test_lib -testplusarg UVM_TIMEOUT=20000000000000 が UVM に対する設定です。

INFO: [COSIM-47] Using XSIM for RTL simulation.
INFO: [COSIM-14] Instrumenting C test bench ...
   Build using "/mnt/usb/XILINX/Vivado/2022.1/Vitis_HLS/2022.1/tps/lnx64/gcc-8.3.0/bin/g++"
   Compiling testbench_multi_apuint.cpp_pre.cpp.tb.cpp
   Compiling apatb_multi_apuint.cpp
   Compiling multi_apuint.cpp_pre.cpp.tb.cpp
   Compiling apatb_multi_apuint_ir.ll
   Generating cosim.tv.exe
INFO: [COSIM-302] Starting C TB testing ...
INFO: [COSIM-333] Generating C post check test bench ...
INFO: [COSIM-12] Generating RTL test bench ...
INFO: [COSIM-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM-323] Starting verilog simulation.
INFO: [COSIM-15] Starting XSIM ...
INFO: [COSIM-316] Starting C post checking ...
multi_out = 0
multi_out = 2
multi_out = 6
multi_out = 12
multi_out = 20
multi_out = 30
multi_out = 42
multi_out = 56
multi_out = 72
multi_out = 90

後半で、xsim + uvm で RTL Simulation を行っています。

Built simulation snapshot multi_apuint

****** xsim v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source xsim.dir/multi_apuint/xsim_script.tcl
# xsim {multi_apuint} -testplusarg UVM_VERBOSITY=UVM_LOW -testplusarg UVM_TESTNAME=multi_apuint_test_lib -testplusarg UVM_TIMEOUT=20000000000000 -autoloadwcfg -tc
lbatch {multi_apuint.tcl}
Time resolution is 1 ps
source multi_apuint.tcl
## run all
UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18601) @ 0: reporter [UVM/RELNOTES]
      (Specify +UVM_NO_RELNOTES to turn off this notice)
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.

  You are using a version of the UVM library that has been compiled

  ***********       IMPORTANT RELEASE NOTES         ************
----------------------------------------------------------------
(C) 2013-2014 NVIDIA Corporation
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2006-2014 Synopsys, Inc.
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2007-2014 Mentor Graphics Corporation
途中略

--- UVM Report Summary ---


$finish called at time : 1425 ns : File "/mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 18699
## quit
INFO: [Common 17-206] Exiting xsim at Sun Jun 26 15:48:57 2022...
multi_out = 0
multi_out = 2
multi_out = 6
multi_out = 12
multi_out = 20
multi_out = 30
multi_out = 42
multi_out = 56
multi_out = 72
multi_out = 90
INFO: [COSIM-1000] *** C/RTL co-simulation finished: PASS ***

result.transaction.rpt は、トランザクション部分のレポートファイルです。

verilog

verilog ディレクトリは、生成された Verilog HDL コードおよびシミュレーションに必要なコマンドファイル(tclファイル)です。DUTのコードだけでなく、テストベンチ関連のファイルも生成されます。

csv_file_dump.svh
dump_file_agent.svh
nodf_module_interface.svh
nodf_module_monitor.svh
sample_agent.svh
sample_manager.svh
multi_apuint.prj
multi_apuint.tcl
multi_apuint.v
multi_apuint.autotb.v
multi_apuint_mul_8ns_8ns_16_1_1.v
multi_apuint_regslice_forward.v
dataflow_monitor.sv
fifo_para.vh
glb.v
sim.sh
run_sim.tcl
check_sim.tcl
dataflow_monitor_API.tcl

は、Random Stall が OFFの時と同じです。これ以外に下記のファイルが追加されています。これらが UVM 関連だと思います。。。

axivip (中は空です)
file_agent
multi_apunit_subsystem (UVMを使って、テストベンチ環境)
svr
svtb
tr_db.log (uvm での Transaction のログファイル)
xsim.covdb/multi_apuint/xsim.covinfo) => xsim コマンドが生成するカバレッジファイル

run_xsim.sh

Random Stall が ON/OFF の時の run_xsim.sh の差分です。xelab コマンドとxsim コマンドの引数が違います。

このコマンドが上記のログファイルの中で実行されています。

xelab コマンド : -L uvm -relax -i ./svr -i ./svtb -i ./file_agent -i ./multi_apuint_subsystem
xsim コマンド : -testplusarg "UVM_VERBOSITY=UVM_LOW" -testplusarg "UVM_TESTNAME=multi_apuint_test_lib" -testplusarg "UVM_TIMEOUT=20000000000000"

xelab コマンドでは、

-L uvm
-relax
-i ./svr
-i ./svtb
-i ./file_agent
-i ./multi_apuint_subsystem

が追加されています。-L uvm でUVMライブラリを使い、svr/svtb/file_agent/multi_apuint_subsystem を include file として指定しています。

-L uvm は、xsim.ini の中で次のように指定されています。Vivado(Vitis_HLSではなく、Vivado)のインストールディレクトリの下のdata が $RDI_DATADIR になります。

uvm=$RDI_DATADIR/xsim/system_verilog/uvm

xelab.log ファイルに、uvm関連のログが出てきます。uvmのディレクトリが何故か？"/proj/xbuilds/SWIP/9999.0_1117_2127/installs/lin64/Vivado/2022.1/" というディレクトリになっていますね。UVMのバージョンは、1.2 です。

xelab.log:Running: /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_multi_apuint_top xil_defaultlib.glbl -Oenable_linking_all_libraries -prj multi_apuint.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_20 -L floating_point_v7_1_14 --lib ieee_proposed=./ieee_proposed -L uvm -relax -i ./svr -i ./svtb -i ./file_agent -i ./multi_apuint_subsystem -s multi_apuint
xelab.log:WARNING: [XSIM 43-4099] "/proj/xbuilds/SWIP/9999.0_1117_2127/installs/lin64/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 4356. Module uvm_pkg doesn't have a timescale but at least one module in design has a timescale.
xelab.log:WARNING: [XSIM 43-4099] "/proj/xbuilds/SWIP/9999.0_1117_2127/installs/lin64/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 4356. Module uvm_pkg doesn't have a timescale but at least one module in design has a timescale.
xelab.log:WARNING: [XSIM 43-4468] File : /proj/xbuilds/SWIP/9999.0_1117_2127/installs/lin64/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv, Line : 25994, RANDC variable size more than 8 bits. This will be treated as a RAND variable instead.
xelab.log:Compiling package uvm.uvm_pkg
Binary file xelab.pb matches

xsim コマンドでは、

-testplusarg "UVM_VERBOSITY=UVM_LOW"
-testplusarg "UVM_TESTNAME=multi_apuint_test_lib"
-testplusarg "UVM_TIMEOUT=20000000000000"

が追加されています。-testplusarg にて、UVM関連のマクロを指定しています。

xsim.log ファイルに、uvm関連のログが出てきます。

UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18601) @ 0: reporter [UVM/RELNOTES]
UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18648) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO ./svtb/multi_apuint_test_lib.sv(30) @ 0: uvm_test_top [uvm_test_top] build_phase done
UVM_INFO ./multi_apuint_subsystem/multi_apuint_env.sv(142) @ 0: uvm_test_top.top_env [uvm_test_top.top_env] set reference model by uvm_config_db
UVM_INFO ./multi_apuint_subsystem/multi_apuint_env.sv(149) @ 0: uvm_test_top.top_env [uvm_test_top.top_env] build_phase done
UVM_INFO ./svr/svr_env.sv(28) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0 [uvm_test_top.top_env.env_master_svr_multi_in0] build_phase is called
UVM_INFO ./svr/svr_master_sequencer.sv(13) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.sqr [uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.sqr] new is called
UVM_INFO ./svr/svr_master_driver.sv(16) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv [uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv] new is called
UVM_INFO ./svr/svr_master_monitor.sv(35) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.mon [uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.mon] new is called
UVM_INFO ./svr/svr_master_driver.sv(26) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv [uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv] build_phase is called
UVM_INFO ./svr/svr_master_monitor.sv(42) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.mon [uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.mon] build_phase is called
UVM_INFO ./svr/svr_env.sv(28) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1 [uvm_test_top.top_env.env_master_svr_multi_in1] build_phase is called
UVM_INFO ./svr/svr_master_sequencer.sv(13) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.sqr [uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.sqr] new is called
UVM_INFO ./svr/svr_master_driver.sv(16) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv [uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv] new is called
UVM_INFO ./svr/svr_master_monitor.sv(35) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.mon [uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.mon] new is called
UVM_INFO ./svr/svr_master_driver.sv(26) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv [uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv] build_phase is called
UVM_INFO ./svr/svr_master_monitor.sv(42) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.mon [uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.mon] build_phase is called
UVM_INFO ./svr/svr_env.sv(28) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out [uvm_test_top.top_env.env_slave_svr_multi_out] build_phase is called
UVM_INFO ./svr/svr_slave_sequencer.sv(13) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.sqr [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.sqr] new is called
UVM_INFO ./svr/svr_slave_driver.sv(16) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv] new is called
UVM_INFO ./svr/svr_slave_monitor.sv(35) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon] new is called
UVM_INFO ./svr/svr_slave_driver.sv(26) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv] build_phase is called
UVM_INFO ./svr/svr_slave_monitor.sv(42) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon] build_phase is called
UVM_INFO ./multi_apuint_subsystem/multi_apuint_env.sv(167) @ 0: uvm_test_top.top_env [uvm_test_top.top_env] connect phase done
UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18752) @ 0: reporter [UVMTOP] UVM testbench topology:
uvm_test_top                                       multi_apuint_test_lib                  -     @353
    env_master_svr_multi_in0                       uvm_env                                -     @389
      m_agt                                        uvm_agent                              -     @621
        drv                                        uvm_driver #(REQ,RSP)                  -     @771
          rsp_port                                 uvm_analysis_port                      -     @790
          seq_item_port                            uvm_seq_item_pull_port                 -     @780
        mon                                        uvm_monitor                            -     @802
          item_collect_port                        uvm_analysis_port                      -     @819
        sqr                                        uvm_sequencer                          -     @632
          rsp_export                               uvm_analysis_export                    -     @641
          seq_item_export                          uvm_seq_item_pull_imp                  -     @759
    env_master_svr_multi_in1                       uvm_env                                -     @402
      m_agt                                        uvm_agent                              -     @839
        drv                                        uvm_driver #(REQ,RSP)                  -     @989
          rsp_port                                 uvm_analysis_port                      -     @1008
          seq_item_port                            uvm_seq_item_pull_port                 -     @998
        mon                                        uvm_monitor                            -     @1020
          item_collect_port                        uvm_analysis_port                      -     @1037
        sqr                                        uvm_sequencer                          -     @850
          rsp_export                               uvm_analysis_export                    -     @859
          seq_item_export                          uvm_seq_item_pull_imp                  -     @977
    env_slave_svr_multi_out                        uvm_env                                -     @412
      s_agt                                        uvm_agent                              -     @1057
        drv                                        uvm_driver #(REQ,RSP)                  -     @1207
          rsp_port                                 uvm_analysis_port                      -     @1226
          seq_item_port                            uvm_seq_item_pull_port                 -     @1216
        mon                                        uvm_monitor                            -     @1238
          item_collect_port                        uvm_analysis_port                      -     @1255
        sqr                                        uvm_sequencer                          -     @1068
          rsp_export                               uvm_analysis_export                    -     @1077
          seq_item_export                          uvm_seq_item_pull_imp                  -     @1195
      rsp_export                                   uvm_analysis_export                    -     @488
      seq_item_export                              uvm_seq_item_pull_imp                  -     @606
      svr_master_multi_in0_imp                     uvm_analysis_imp_svr_master_multi_in0  -     @449
      svr_master_multi_in1_imp                     uvm_analysis_imp_svr_master_multi_in1  -     @459
      svr_slave_multi_out_imp                      uvm_analysis_imp_svr_slave_multi_out   -     @469
    env_master_svr_multi_in0                       uvm_env                                -     @389
    env_master_svr_multi_in1                       uvm_env                                -     @402
    env_slave_svr_multi_out                        uvm_env                                -     @412
UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(20867) @ 0: reporter [UVM/COMP/NAMECHECK] This implementation of the component name checks requires DPI to be enabled
UVM_INFO ./multi_apuint_subsystem/multi_apuint_env.sv(172) @ 0: uvm_test_top.top_env [uvm_test_top.top_env] multi_apuint_env is running
UVM_INFO ./svr/svr_slave_monitor.sv(63) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon] run_phase is called
UVM_INFO ./svr/svr_slave_driver.sv(35) @ 0: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv [uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv] run_phase is called
UVM_INFO ./svr/svr_master_driver.sv(36) @ 0: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv [uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv] run_phase is called
UVM_INFO ./svr/svr_master_driver.sv(36) @ 0: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv [uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv] run_phase is called
UVM_INFO ./svtb/multi_apuint_subsys_test_sequence_lib.sv(46) @ 0: uvm_test_top.top_env.multi_apuint_virtual_sqr@@multi_apuint_subsys_test_sequence_lib [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib] get reference model by uvm_config_db
UVM_INFO ./svtb/multi_apuint_subsys_test_sequence_lib.sv(48) @ 0: uvm_test_top.top_env.multi_apuint_virtual_sqr@@multi_apuint_subsys_test_sequence_lib [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib] body is called
UVM_INFO ./svtb/multi_apuint_subsys_test_sequence_lib.sv(51) @ 0: uvm_test_top.top_env.multi_apuint_virtual_sqr@@multi_apuint_subsys_test_sequence_lib [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib] starting_phase not null
UVM_INFO ./svr/svr_master_sequence.sv(29) @ 1145000: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.sqr@@multi_apuint_subsys_test_sequence_lib.svr_port_multi_in0_seq [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_in0_seq] body is called
UVM_INFO ./svr/svr_master_sequence.sv(29) @ 1145000: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.sqr@@multi_apuint_subsys_test_sequence_lib.svr_port_multi_in1_seq [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_in1_seq] body is called
UVM_INFO ./svr/svr_slave_sequence.sv(24) @ 1145000: uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.sqr@@multi_apuint_subsys_test_sequence_lib.svr_port_multi_out_seq [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_out_seq] body is called
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1155000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1155000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1165000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1165000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1175000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1175000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1175000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1175000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1175000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1205000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1205000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1205000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1205000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1205000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1215000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1215000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1215000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1225000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1225000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1225000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1235000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1235000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1245000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1245000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1275000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1275000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1275000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1275000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1275000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1285000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1285000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1285000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1295000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1295000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1295000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1305000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1305000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1315000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1315000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1325000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1325000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(81) @ 1325000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_ready_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(128) @ 1325000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_READY
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1325000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./svr/svr_master_sequence.sv(91) @ 1325000: uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.sqr@@multi_apuint_subsys_test_sequence_lib.svr_port_multi_in1_seq [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_in1_seq] send all TVs done
UVM_INFO ./svr/svr_master_sequence.sv(91) @ 1335000: uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.sqr@@multi_apuint_subsys_test_sequence_lib.svr_port_multi_in0_seq [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_in0_seq] send all TVs done
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1345000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1345000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1345000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(120) @ 1355000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event DUT2TB_AP_DONE
UVM_INFO ./multi_apuint_subsystem/multi_apuint_reference_model.sv(103) @ 1355000: uvm_test_top.top_env.refm [uvm_test_top.top_env.refm] trigger event ap_done_for_nexttrans
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(55) @ 1355000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive ap_done_for_nexttrans and do axim dump
UVM_INFO ./svtb/multi_apuint_subsys_test_sequence_lib.sv(146) @ 1355000: uvm_test_top.top_env.multi_apuint_virtual_sqr@@multi_apuint_subsys_test_sequence_lib [uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib] autotb finished
UVM_INFO ./multi_apuint_subsystem/multi_apuint_scoreboard.sv(60) @ 1355000: uvm_test_top.top_env.subsys_mon.scbd [uvm_test_top.top_env.subsys_mon.scbd] receive FINISH
UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(19968) @ 1425000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(13673) @ 1425000: reporter [UVM/REPORT/SERVER] [uvm_test_top.top_env.subsys_mon.scbd]    11
[uvm_test_top.top_env.refm]    40
[uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_out_seq]     1
[uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_in1_seq]     2
[uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib.svr_port_multi_in0_seq]     2
[uvm_test_top.top_env.multi_apuint_virtual_sqr.multi_apuint_subsys_test_sequence_lib]     4
[uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.sqr]     1
[uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.mon]     3
[uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.drv]     3
[uvm_test_top.top_env.env_slave_svr_multi_out]     1
[uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.sqr]     1
[uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.mon]     2
[uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.drv]     3
[uvm_test_top.top_env.env_master_svr_multi_in1]     1
[uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.sqr]     1
[uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.mon]     2
[uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.drv]     3
[uvm_test_top.top_env.env_master_svr_multi_in0]     1
[uvm_test_top.top_env]     4
[uvm_test_top]     1
$finish called at time : 1425 ns : File "/mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv" Line 18699

また、tr_db.log ファイルにも uvm という文字があります。

  CREATE_STREAM @0 {NAME:multi_apuint_subsys_test_sequence_lib T:Transactions SCOPE:uvm_test_top.top_env.multi_apuint_virtual_sqr STREAM:1322}
  CREATE_STREAM @1145000 {NAME:multi_apuint_subsys_test_sequence_lib T:Transactions SCOPE:uvm_test_top.top_env.env_master_svr_multi_in0.m_agt.sqr STREAM:1432}
  CREATE_STREAM @1145000 {NAME:multi_apuint_subsys_test_sequence_lib T:Transactions SCOPE:uvm_test_top.top_env.env_master_svr_multi_in1.m_agt.sqr STREAM:1448}
  CREATE_STREAM @1145000 {NAME:multi_apuint_subsys_test_sequence_lib T:Transactions SCOPE:uvm_test_top.top_env.env_slave_svr_multi_out.s_agt.sqr STREAM:1462}

multi_apuint.prj

VivadoのProjectファイル multi_apuint.prj の違いをみてみます。Random Stall OFFだと、次のようになります。

sv work "glbl.v"
sv xil_defaultlib "multi_apuint.autotb.v"
sv xil_defaultlib "multi_apuint.v"
sv xil_defaultlib "multi_apuint_mul_8ns_8ns_16_1_1.v"
sv xil_defaultlib "multi_apuint_regslice_forward.v"
sv xil_defaultlib "dataflow_monitor.sv"

Random Stall ON だと、次のようになります。

sv xil_defaultlib "glbl.v"
sv xil_defaultlib "multi_apuint.autotb.v"
sv xil_defaultlib "multi_apuint.v"
sv xil_defaultlib "multi_apuint_mul_8ns_8ns_16_1_1.v"
sv xil_defaultlib "multi_apuint_regslice_forward.v"
sv xil_defaultlib "dataflow_monitor.sv"
sv xil_defaultlib "./file_agent/file_agent_pkg.sv"
sv xil_defaultlib "./svr/svr_pkg.sv"
sv xil_defaultlib "./svr/svr_if.sv"
sv xil_defaultlib "./multi_apuint_subsystem/multi_apuint_subsystem_pkg.sv"
sv xil_defaultlib "./svtb/misc_interface.sv"
sv xil_defaultlib "./svtb/sv_module_top.sv"

違いは、下記の部分です。 ```` sv xil_defaultlib "./file_agent/file_agent_pkg.sv" sv xil_defaultlib "./svr/svr_pkg.sv" sv xil_defaultlib "./svr/svr_if.sv" sv xil_defaultlib "./multi_apuint_subsystem/multi_apuint_subsystem_pkg.sv" sv xil_defaultlib "./svtb/misc_interface.sv" sv xil_defaultlib "./svtb/sv_module_top.sv"

これは、xelab コマンドの下記の部分に対応しています。

- -i ./svr
- -i ./svtb
- -i ./file_agent
- -i ./multi_apuint_subsystem

# おわりに

次回以降は、uvm に関する上記のファイルをみていきます。

Vengineerの戯言

人生は短いけど、長いです。人生を楽しみましょう！

Xilinx Vitis の中を調べる(その7)