Mentor : ESL to RTL verification flow with UVM

Verification Engineerの戯言 : Twitter
SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

Mentor Graphics Addresses 28nm and 3D-IC Requirements in TSMC Reference Flow 12によると、Mentorは

引用
    The Vista?? platform supports functional validation and power estimation 
      based on TSMC iPPA process node value characterization, 
      and enables OS booting and early validation of application software 
      on a Virtual TLM Platform. 

    The Certe?? Testbench Studio product provides automated 
      Universal Verification Methodology (UVM) testbench creation, 
      saving time and reducing errors. 

    The Catapult?? C high-level synthesis tool supports SystemC 
      and incremental synthesis, which is demonstrated on a complete, 
      multi-block, hardware accelerator component. 

    The Catapult C tool’s generated RTL, including AXI interfaces, 
      is combined with the Questa?? Verification IP and a TLM Virtual Platform 
      running in Vista to provide a hybrid TLM and RTL simulation. 

    The Questa Ultra Platform provides an ESL to RTL verification flow 
      with UVM that supports TLM platform and model reuse, 
      test plan tracking and accelerated coverage closure. 

    Questa Codelink provides HW/SW co-verification to greatly reduce debug time 
      when running system tests on an embedded processor.

と、MentorのESL関連ツールが勢揃いです。

Thomas Bollaert’s BlogにもMentor ESL in TSMC Reference Flow 12がアップされました。
ここでも取り上げています。

先日の「Questaが可能にする機能検証改革」セミナーでは、
これらのツールの説明がありました。ただし、CerteとCatapultは除く。

検証では、

　　Virtual Platform => Vista
　　Verification     => Questa Ultra
    HW-SW Debug      => Questa Codelink

になります。

さあ、どうなるのでしょうか？

検証、Verification、Mentor

P.S
Certeは良いツールだと思うのだが、なぜ、うけないのだろうか？　教えてちょ！