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Xilinx Vitis の中を調べる(その5)

はじめに

Xilinx Vitis の中を調べるのその５。

今回は、C/RTL cosimulation 実行時の RTL simulation 用に生成された sim/verilog ディレクトリをみてみます。

sim/verilog

下記のようなファイルが生成されます。run_xsim.sh が xsim でのシミュレーション用コマンドのようです。

  • check_sim.tcl
  • csv_file_dump.svh
  • dataflow_monitor.sv
  • dataflow_monitor_API.tcl
  • dump_file_agent.svh
  • fifo_para.vh
  • glbl.v
  • multi_apuint.autotb.v
  • multi_apuint.performance.result.transaction.xml
  • multi_apuint.prj
  • multi_apuint.protoinst
  • multi_apuint.result.lat.rb
  • multi_apuint.tcl
  • multi_apuint.v
  • multi_apuint_dataflow_ana.wcfg
  • multi_apuint_mul_8ns_8ns_16_1_1.v
  • multi_apuint_regslice_forward.v
  • nodf_module_interface.svh
  • nodf_module_monitor.svh
  • run_sim.tcl
  • run_xsim.sh
  • sample_agent.svh
  • sample_manager.svh
  • sim.sh
  • xelab.log
  • xelab.pb
  • xsim.dir (ディレクトリ)
  • xsim.ini
  • xsim.jou
  • xsim.log

run_xsim.sh

run_xsim.sh を実行するには、下記のファイルが必要のようです。

  • csv_file_dump.svh
  • dump_file_agent.svh
  • nodf_module_interface.svh
  • nodf_module_monitor.svh
  • sample_agent.svh
  • sample_manager.svh
  • multi_apuint.prj
  • multi_apuint.tcl
  • multi_apuint.v
  • multi_apuint.autotb.v
  • multi_apuint_mul_8ns_8ns_16_1_1.v
  • multi_apuint_regslice_forward.v
  • dataflow_monitor.sv
  • fifo_para.vh
  • glb.v

run_xsim.sh を実行すると、次のようなメッセージが出力されます。

Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: /mnt/usb/XILINX/Vivado/2022.1/Vivado/2022.1/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_multi_apuint_top glbl -Oenable_linking_all_libraries -prj multi_apuint.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_20 -L floating_point_v7_1_14 --lib ieee_proposed=./ieee_proposed -s multi_apuint
Multi-threading is on. Using 6 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue.  If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
    CPATH
    LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/multi_apuint.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_multi_apuint_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/multi_apuint.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multi_apuint
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/multi_apuint_mul_8ns_8ns_16_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multi_apuint_mul_8ns_8ns_16_1_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/multi_apuint_regslice_forward.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multi_apuint_regslice_forward
INFO: [VRFC 10-311] analyzing module multi_apuint_regslice_forward_w1
INFO: [VRFC 10-311] analyzing module multi_apuint_regslice_obuf
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/dataflow_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dataflow_monitor
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.multi_apuint_mul_8ns_8ns_16_1_1(...
Compiling module xil_defaultlib.multi_apuint_regslice_obuf(W=9)
Compiling module xil_defaultlib.multi_apuint_regslice_forward(Da...
Compiling module xil_defaultlib.multi_apuint_regslice_obuf(W=17)
Compiling module xil_defaultlib.multi_apuint_regslice_forward(Da...
Compiling module xil_defaultlib.multi_apuint
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_multi_apuint_top
Compiling module work.glbl
Built simulation snapshot multi_apuint

****** xsim v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source xsim.dir/multi_apuint/xsim_script.tcl
# xsim {multi_apuint} -autoloadwcfg -tclbatch {multi_apuint.tcl}
Time resolution is 1 ps
source multi_apuint.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 10 [0.00%] @ "125000"
// RTL Simulation : 1 / 10 [50.00%] @ "165000"
// RTL Simulation : 2 / 10 [50.00%] @ "175000"
// RTL Simulation : 3 / 10 [50.00%] @ "185000"
// RTL Simulation : 4 / 10 [50.00%] @ "195000"
// RTL Simulation : 5 / 10 [50.00%] @ "205000"
// RTL Simulation : 6 / 10 [50.00%] @ "215000"
// RTL Simulation : 7 / 10 [50.00%] @ "225000"
// RTL Simulation : 8 / 10 [50.00%] @ "235000"
// RTL Simulation : 9 / 10 [50.00%] @ "245000"
// RTL Simulation : 10 / 10 [100.00%] @ "255000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 315 ns : File "/mnt/c/Users/haray/home/src/vitis/multi_apuint/solution1/sim/a/multi_apuint.autotb.v" Line 381
## quit
INFO: [Common 17-206] Exiting xsim at Sun Jun 26 14:58:30 2022...

run_xsim.sh コマンドを実行したことにより生成されたファイルは以下のようになりました。

  • multi_apuint.performance.result.transaction.xml
  • multi_apuint.result.lat.rb
  • multi_apuint_dataflow_ana.wcfg
  • xelab.log
  • xelab.pb
  • xsim.dir (ディレクトリ)
  • xsim.jou
  • xsim.log

以下の6個のファイルはどのような目的で使われるのでしょうか？

  • sim.sh
  • run_sim.tcl (sim.sh の中で vitis_hls コマンドの引数で使われる)
  • check_sim.tcl (run_sim.tcl の中から呼ばれる)
  • dataflow_monitor_API.tcl (run_sim.tcl の中から呼ばれる)

上記のことから、run_xsim.sh ではなく、sim.sh を実行すればいいようです。run_sim.tcl の中で、

  • mrapc/cosim.tv.exe
  • mrapc_pc/cosim.pc.exe

を実行して、check_sim.tcl の中で2つのログファイルを比較しているようです。

  • multi_apuint.protoinst
  • multi_apuint_dataflow_ana.wcfg
  • xsim.ini

の3つは、何故あるか？わかりません。

おわりに

次回は、テストベンチがどのようになっているのかを調べてみます。