はじめに
Xilinx Vitis の中を調べるのその18。
m_axi にして、Random Stall をONにして、生成されたテストベンチ環境をみています。
svtb/sv_module_top.sv
svtb/sv_module_top.sv の中は、下記のようになっています。
テストシナリオは?
テストシナリオは、sim/verilog/svtb/multi_apuint_subsys_test_sequence_lib.sv では、下記のように、
- axi_slave_BUS_A_seq
- axi_slave_BUS_B_seq
- axi_slave_BUS_C_seq
- axi_master_wr_control_seq
がそれぞれ、上記の図のポートに対応しています。
fork begin //axi slave sequence. loop delays `uvm_create_on(axi_slave_BUS_A_seq, p_sequencer.BUS_A_sqr); axi_slave_BUS_A_seq.misc_if = refm.misc_if; axi_slave_BUS_A_seq.ap_done = refm.ap_done_for_nexttrans ; axi_slave_BUS_A_seq.ap_ready = refm.ap_ready_for_nexttrans ; axi_slave_BUS_A_seq.finish = refm.finish ; axi_slave_BUS_A_seq.isusr_delay = axi_pkg::NO_DELAY; `uvm_send(axi_slave_BUS_A_seq); end begin //axi slave sequence. loop delays `uvm_create_on(axi_slave_BUS_B_seq, p_sequencer.BUS_B_sqr); axi_slave_BUS_B_seq.misc_if = refm.misc_if; axi_slave_BUS_B_seq.ap_done = refm.ap_done_for_nexttrans ; axi_slave_BUS_B_seq.ap_ready = refm.ap_ready_for_nexttrans ; axi_slave_BUS_B_seq.finish = refm.finish ; axi_slave_BUS_B_seq.isusr_delay = axi_pkg::NO_DELAY; `uvm_send(axi_slave_BUS_B_seq); end begin //axi slave sequence. loop delays `uvm_create_on(axi_slave_BUS_C_seq, p_sequencer.BUS_C_sqr); axi_slave_BUS_C_seq.misc_if = refm.misc_if; axi_slave_BUS_C_seq.ap_done = refm.ap_done_for_nexttrans ; axi_slave_BUS_C_seq.ap_ready = refm.ap_ready_for_nexttrans ; axi_slave_BUS_C_seq.finish = refm.finish ; axi_slave_BUS_C_seq.isusr_delay = axi_pkg::NO_DELAY; `uvm_send(axi_slave_BUS_C_seq); end begin int control_page_idx_bak; `uvm_create_on(axi_master_wr_control_seq, p_sequencer.control_sqr); axi_master_wr_control_seq.misc_if = refm.misc_if; axi_master_wr_control_seq.ap_done = refm.ap_done_for_nexttrans ; axi_master_wr_control_seq.ap_ready = refm.ap_ready_for_nexttrans ; axi_master_wr_control_seq.finish = refm.finish ; axi_master_wr_control_seq.isusr_delay = axi_pkg::NO_DELAY; for(int i=0; i<10; i++) begin logic[63:0] data64bit[$]; logic[32-1:0] databusbit[$]; data64bit.delete(); databusbit.delete(); axi_master_wr_control_seq.StableAxiliteNoUpdate=0; for(int j=0; j < (64+32-1)/32; j++) begin data64bit.push_back( ((refm.mem_blk_pages_BUS_A.maxi_bundlevar_offset["multi_in0"]+r efm.mem_blk_pages_BUS_A.page_ofst[refm.mem_blk_pages_BUS_A.rd_page_idx])>>(j*32)) & (2**32-1) ); end; foreach(data64bit[i]) databusbit[i]=data64bit[i][32-1:0]; axi_master_wr_control_seq.StableAxiliteNoUpdate=1; axi_master_wr_control_seq.datamerge_inavg(databusbit, 0, 16, 1); data64bit.delete(); databusbit.delete(); axi_master_wr_control_seq.StableAxiliteNoUpdate=0; for(int j=0; j < (64+32-1)/32; j++) begin data64bit.push_back( ((refm.mem_blk_pages_BUS_B.maxi_bundlevar_offset["multi_in1"]+r efm.mem_blk_pages_BUS_B.page_ofst[refm.mem_blk_pages_BUS_B.rd_page_idx])>>(j*32)) & (2**32-1) ); end; foreach(data64bit[i]) databusbit[i]=data64bit[i][32-1:0]; axi_master_wr_control_seq.StableAxiliteNoUpdate=1; axi_master_wr_control_seq.datamerge_inavg(databusbit, 0, 28, 1); data64bit.delete(); databusbit.delete(); axi_master_wr_control_seq.StableAxiliteNoUpdate=0; for(int j=0; j < (64+32-1)/32; j++) begin data64bit.push_back( ((refm.mem_blk_pages_BUS_C.maxi_bundlevar_offset["multi_out"]+r efm.mem_blk_pages_BUS_C.page_ofst[refm.mem_blk_pages_BUS_C.rd_page_idx])>>(j*32)) & (2**32-1) ); end; foreach(data64bit[i]) databusbit[i]=data64bit[i][32-1:0]; axi_master_wr_control_seq.StableAxiliteNoUpdate=1; axi_master_wr_control_seq.datamerge_inavg(databusbit, 0, 40, 1); `uvm_send(axi_master_wr_control_seq); @(posedge refm.misc_if.clock); //wait address 2 rsp done @(posedge refm.misc_if.clock); refm.write_data_finish_control = 1; `uvm_info("control data writting thread", $sformatf("%0dth(total 10): waiting for all wr ite data finish event",i), UVM_LOW) wait(refm.allaxilite_write_data_finish.triggered); refm.write_data_finish_control = 0; `uvm_info("control wait for ap_ready for next trans", $sformatf("%0dth(total 10): begin to wait" ,i), UVM_LOW) wait(refm.dut2tb_ap_ready.triggered); #0.01; //make sure mem incr_rd_page_idx is called first end end
おわりに
s_axilite に対して、m_axi では、misc_if が ap_XXX から axi_if になりました。
次回は、mode=s_axilite を追加するとどのようになるかをみてみます。