UVM: Ready, Set, Deploy!

Verification Evangelistの戯言 : Twitter
SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

たぶん、DVCon2012の時のビデオだと思うのですが、UVM:Read, Set, Deploy!なるものがアップされています。
ただし、ユーザー登録が必要。

内容は、こんな感じ。(引用)

Part 1: Base Classes in UVM
    Tom Fitzpatrick, Mentor Graphics
    Part 2: Communication and Sequences
    John Aynsley, Doulos
    Part 3: Customizing Your UVM Environment
    Kathleen Meade, Cadence Design Systems
    Part 4: Register Modeling in UVM
    Adiel Khan, Synopsys

Real-life user experiences:

    Part 1: Getting Started with UVM
    Vanessa Cooper, Verilab
    Part 2: Stacking Verification Components in UVM
    Stephen D'Onofrio, Paradigm Works
    Peter J. D'Antonio, The MITRE Corp.
    Part 3: OVM to UVM Transition
    John Fowler, Advanced Micro Devices
    Justin Refice, Advanced Micro Devices
    Part 4: VC Building Blocks with UVM
    Mark Strickland, Cisco Systems

いかがでしょうか？

検証、Verification、UVM