AldecのRiviera-PRO 2012.06がリリースされました。
Aldec、頑張っていますね。
リリースノートから引用です。
Core Simulation Engine: * Latest verification libraries – UVM 1.1b, VMM 1.1.1a, OS-VVM 2.3.1 * Simulation performance improvements – SystemVerilog simulation now up to 24% faster! * Stability on large designs – over 100 bugs resolved! * New language constructs in SystemVerilog’2009 and VHDL’2008 Framework and Productivity: * Project tasks management – a new Tasks window displays current list of tasks assigned within a project * Waveform enhanced for displaying of composite objects (arrays, virtual groups) * New options for waveform comparison command (delta accuracy, marking values as identical) * Auto-templates based on current selection, UVM-specific code templates * Verilog hierarchical references in Advanced Dataflow, and printing of Advanced Dataflow contents * Design files management – file-level properties (compilation settings) * New commands for ACDB (Aldec UCIS-compatible Coverage Database) files manipulation 3rd Party Interfaces: * Agilent SystemVue co-simulation interfaces – link to RF System simulator * Tanner EDA HiPer Simulation A/MS – Analog/Mixed Signal simulation (SPICE, Verilog-AMS) * Enables developing custom IPs that target Xilinx Zynq-7000s devices (AXI4 BFM simulation) * Provides the latest precompiled simulation libraries for Altera and Xilinx FPGAs * Compatible with the latest release of Xilinx Vivado™ Design Suite
24%速くなるのは、Linux版です。
検証、Verification、Aldec
