VERIFICATION HORIZONS, Oct. 2012がアップされています。
引用
ST-Ericsson Speeds Time to Functional Verification Closure with Questa Verification Platform
by Rachida El IDRISSI, ST-Ericsson
The Top Five Formal Verification Applications
by Roger Sabbagh, Mentor Graphics
Three Steps to Unified SoC Design and Verification
by Shabtay Matalon and Mark Peryer, Mentor Graphics
Evolution of UPF: Getting Better All the Time
by Erich Marschner, Product Manager, Questa Power Aware Simulation, Mentor Graphics
Improving Analog/Mixed-Signal Verification Productivity
by Ahmed Eisawy, Mentor Graphics
VHDL-2008: Why It Matters
by Jim Lewis, SynthWorks VHDL Training
検索、Verification、Mentor
