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Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
この論文では、以下のような内容のようです。
引用します • It provides a formal model for the ILA (§ 3). This addresses critical modeling issues in both processors and accelerators including gaps in previous ISA formal models. Top-down this model provides a formal specification for use in hardware verification, and bottom-up an abstraction for use in software/hardware co-verification that is uniform across accelerators and processors. • It supports hierarchy (§ 3.2) in modeling instructions which is missing from the earlier formal ISA models [59]. In particular, it makes the important distinction between hierarchy in the specification and hierarchy in the implementation. • It demonstrates the applicability of the ILA model through several case studies on accelerators (AES, RBM, Gaussian Blur) and the RISC-V Rocket processor (§ 4). • It demonstrates the value in verification across models – between two ILAs, and between ILA and FSM models – through successful case studies (§ 5), including finding a bug in the RISC-V Rocket processor core. Verifying FSM implementations against ILA specifications provides the basis for ILA-compatible accelerator replacement.
おー、Halide だよ。
