はじめに
Twitter に SiliconCompiler.com のツイートを見つけました
I am alive! https://t.co/YEWW0yqffk pic.twitter.com/XFWnb20INl
— SiliconCompiler (@siliconcompiler) 2021年12月4日
SiliconCompiler
サイトは、こちら。
作っているのは、Andreas Olofsson さんです。Zero ASICの人です。
このブログでも依然紹介した Adapteva の開発者です。
インストールしてみた
$ python -m pip install siliconcompiler
ちょっと時間がかかった
echo "module flipflop (input clk, d, output reg out); \ > always @ (posedge clk) out <= d; endmodule"> flipflop.v
簡単な flipflop を Verilog HDL にして、
$ sc flipflop.v -remote ____ _ _ _ ____ _ _ / ___|(_) (_) ___ ___ _ __ / ___|___ _ __ ___ _ __ (_) | ___ _ __ \___ \| | | |/ __/ _ \| '_ \ | | / _ \| '_ ` _ \| '_ \| | |/ _ \ '__| ___) | | | | (_| (_) | | | | | |__| (_) | | | | | | |_) | | | __/ | |____/|_|_|_|\___\___/|_| |_| \____\___/|_| |_| |_| .__/|_|_|\___|_| |_| Authors: Andreas Olofsson, William Ransohoff, Noah Moroze, Zachary Yedidia Version: 0.1.0 -------------------------------------------------------------------------------- | INFO | job0 | --- | - | Setting commandline arguments | INFO | job0 | --- | - | Loading target 'asicflow_freepdk45' | INFO | job0 | --- | - | Loading function 'setup_flow' from module 'asicflow' | INFO | job0 | --- | - | Loading function 'setup_pdk' from module 'freepdk45' | INFO | job0 | --- | - | Operating in 'asic' mode | ERROR | job0 | --- | - | Could not find remote server configuration - please run "sc-configure" and enter your server address and credentials.
アカウント作らないとダメっぽい。-remote を削除してみたら、なんか、動いている
sc flipflop.v
____ _ _ _ ____ _ _
/ ___|(_) (_) ___ ___ _ __ / ___|___ _ __ ___ _ __ (_) | ___ _ __
\___ \| | | |/ __/ _ \| '_ \ | | / _ \| '_ ` _ \| '_ \| | |/ _ \ '__|
___) | | | | (_| (_) | | | | | |__| (_) | | | | | | |_) | | | __/ |
|____/|_|_|_|\___\___/|_| |_| \____\___/|_| |_| |_| .__/|_|_|\___|_|
|_|
Authors: Andreas Olofsson, William Ransohoff, Noah Moroze, Zachary Yedidia
Version: 0.1.0
--------------------------------------------------------------------------------
| INFO | job0 | --- | - | Setting commandline arguments
| INFO | job0 | --- | - | Loading target 'asicflow_freepdk45'
| INFO | job0 | --- | - | Loading function 'setup_flow' from module 'asicflow'
| INFO | job0 | --- | - | Loading function 'setup_pdk' from module 'freepdk45'
| INFO | job0 | --- | - | Operating in 'asic' mode
| INFO | job0 | import | 0 | Waiting for inputs...
| INFO | job0 | syn | 0 | Waiting for inputs...
| INFO | job0 | floorplan | 0 | Waiting for inputs...
| INFO | job0 | physyn | 0 | Waiting for inputs...
| INFO | job0 | place | 0 | Waiting for inputs...
| INFO | job0 | cts | 0 | Waiting for inputs...
| INFO | job0 | route | 0 | Waiting for inputs...
| INFO | job0 | export | 0 | Waiting for inputs...
| INFO | job0 | dfm | 0 | Waiting for inputs...
| INFO | job0 | import | 0 | Collecting input sources
| INFO | job0 | import | 0 | Copying /mnt/c/Users/haray/home/tmp/siliconcompiler/flipflop.v to 'inputs' directory
| INFO | job0 | import | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/flipflop/job0/import/0/sc_manifest.tcl
| INFO | job0 | import | 0 | Running in /mnt/c/Users/haray/home/tmp/siliconcompiler/build/flipflop/job0/import/0
| INFO | job0 | import | 0 | surelog -parse /mnt/c/Users/haray/home/tmp/siliconcompiler/flipflop.v -top flipflop +libext+.sv
[INF:CM0023] Creating log file ./slpp_all/surelog.log.
[WRN:PA0205] /mnt/c/Users/haray/home/tmp/siliconcompiler/flipflop.v:1: No timescale set for "flipflop".
[INF:CP0300] Compilation...
[INF:CP0303] /mnt/c/Users/haray/home/tmp/siliconcompiler/flipflop.v:1: Compile module "work@flipflop".
[INF:CP0302] /home/vengineer/.local/lib/python3.8/site-packages/siliconcompiler/tools/surelog/bin/../lib/surelog/sv/builtin.sv:4: Compile class "work@mailbox".
[INF:CP0302] /home/vengineer/.local/lib/python3.8/site-packages/siliconcompiler/tools/surelog/bin/../lib/surelog/sv/builtin.sv:33: Compile class "work@process".
[INF:CP0302] /home/vengineer/.local/lib/python3.8/site-packages/siliconcompiler/tools/surelog/bin/../lib/surelog/sv/builtin.sv:58: Compile class "work@semaphore".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /mnt/c/Users/haray/home/tmp/siliconcompiler/flipflop.v:1: Top level module "work@flipflop".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
[INF:UH0708] Writing UHDM DB: ./slpp_all//surelog.uhdm...
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 1
[ NOTE] : 5
| INFO | job0 | import | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/flipflop/job0/import/0/outputs/flipflop.pkg.json
| INFO | job0 | syn | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/flipflop/job0/syn/0/sc_manifest.tcl
| INFO | job0 | syn | 0 | Running in /mnt/c/Users/haray/home/tmp/siliconcompiler/build/flipflop/job0/syn/0
| INFO | job0 | syn | 0 | yosys -c /home/vengineer/.local/lib/python3.8/site-packages/siliconcompiler/tools/yosys/sc_syn.tcl
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9 (git sha1 1979e0b)
echo on
yosys> read_verilog -sv inputs/flipflop.v
1. Executing Verilog-2005 frontend: inputs/flipflop.v
Parsing SystemVerilog input from `inputs/flipflop.v' to AST representation.
Generating RTLIL representation for module `\flipflop'.
Successfully finished Verilog frontend.
yosys> chparam -list
flipflop:
yosys> read_liberty -lib None
2. Executing Liberty frontend.
ERROR: Can't open input file `None' for reading: No such file or directory
| WARNING | job0 | syn | 0 | Command failed. See log file /mnt/c/Users/haray/home/tmp/siliconcompiler/build/flipflop/job0/syn/0/syn.log
| ERROR | job0 | syn | 0 | Halting step 'syn' index '0' due to errors.
| ERROR | job0 | floorplan | 0 | Halting step due to previous error in syn0
| ERROR | job0 | floorplan | 0 | Halting step 'floorplan' index '0' due to errors.
| ERROR | job0 | physyn | 0 | Halting step due to previous error in floorplan0
| ERROR | job0 | physyn | 0 | Halting step 'physyn' index '0' due to errors.
| ERROR | job0 | place | 0 | Halting step due to previous error in physyn0
| ERROR | job0 | place | 0 | Halting step 'place' index '0' due to errors.
| ERROR | job0 | cts | 0 | Halting step due to previous error in place0
| ERROR | job0 | cts | 0 | Halting step 'cts' index '0' due to errors.
| ERROR | job0 | route | 0 | Halting step due to previous error in cts0
| ERROR | job0 | route | 0 | Halting step 'route' index '0' due to errors.
| ERROR | job0 | dfm | 0 | Halting step due to previous error in route0
| ERROR | job0 | dfm | 0 | Halting step 'dfm' index '0' due to errors.
| ERROR | job0 | export | 0 | Halting step due to previous error in dfm0
| ERROR | job0 | export | 0 | Halting step 'export' index '0' due to errors.
| ERROR | job0 | --- | - | Run() failed, exiting! See previous errors.
エラーになった、どうやら合成ツール (Yosys の libertyの読み込みでエラーになっているっぽい)
github.com から clone してみたら、できた
git clone https://github.com/siliconcompiler/siliconcompiler cd siliconcompiler git submodule update --init --recursive third_party/tools/openroad git submodule update --init --recursive third_party/tools/surelog pip install -r requirements.txt python -m pip install -e .
後、surelog と openRoad をビルド & インストールすることで、実行できました。
cd third_party/tools/surelog
make
make install
cd third_party/tools/openroad sudo service docker start bash ./build_openroad.sh
Quick Start の heatbeat に対して、
cat heatbeat.sdc create_clock -name clk -period 1 [get_ports {clk}]
import siliconcompiler # import python package chip = siliconcompiler.Chip() # create chip object chip.set('source', 'heartbeat.v') # define list of source files chip.set('design', 'heartbeat') # set top module chip.set('constraint', 'heartbeat.sdc') # set constraints file chip.target('freepdk45') # load predefined target #chip.set('remote', False) # start of flowgraph setup chip.run() # run compilation chip.summary() # print results summary chip.show() # show layout file
上記の heatbeat.py の chip.target("asicflow_freepdk45") だと、yosys でエラーになります。これを下記のように、 chip.target("freepdk45") にすると、エラーは無くなりました。
python heartbeat.py | INFO | job0 | --- | - | Loading target 'asicflow_freepdk45' | INFO | job0 | --- | - | Loading function 'setup_flow' from module 'asicflow' | INFO | job0 | --- | - | Loading function 'setup_pdk' from module 'freepdk45' | INFO | job0 | --- | - | Operating in 'asic' mode | INFO | job0 | import | 0 | Waiting for inputs... | INFO | job0 | floorplan | 0 | Waiting for inputs... | INFO | job0 | syn | 0 | Waiting for inputs... | INFO | job0 | physyn | 0 | Waiting for inputs... | INFO | job0 | place | 0 | Waiting for inputs... | INFO | job0 | dfm | 0 | Waiting for inputs... | INFO | job0 | cts | 0 | Waiting for inputs... | INFO | job0 | export | 0 | Waiting for inputs... | INFO | job0 | import | 0 | Collecting input sources | INFO | job0 | route | 0 | Waiting for inputs... | INFO | job0 | import | 0 | Copying /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v to 'inputs' directory | INFO | job0 | import | 0 | Copying /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.sdc to 'inputs' directory | INFO | job0 | import | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/import/0/sc_manifest.tcl | INFO | job0 | import | 0 | Running in /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/import/0 | INFO | job0 | import | 0 | surelog -parse /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v -top heartbeat +libext+.sv [INF:CM0023] Creating log file ./slpp_all/surelog.log. [WRN:PA0205] /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v:1: No timescale set for "heartbeat". [INF:CP0300] Compilation... [INF:CP0303] /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v:1: Compile module "work@heartbeat". [INF:CP0302] builtin.sv:4: Compile class "work@mailbox". [INF:CP0302] builtin.sv:33: Compile class "work@process". [INF:CP0302] builtin.sv:58: Compile class "work@semaphore". [INF:EL0526] Design Elaboration... [NTE:EL0503] /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v:1: Top level module "work@heartbeat". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 1. [NTE:EL0510] Nb instances: 1. [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... [INF:UH0708] Writing UHDM DB: ./slpp_all//surelog.uhdm... [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 1 [ NOTE] : 5 | INFO | job0 | import | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/import/0/outputs/heartbeat.pkg.json Traceback (most recent call last): File "/mnt/c/Users/haray/home/tmp/siliconcompiler/siliconcompiler/siliconcompiler/core.py", line 2684, in _runtask_safe self._runtask(step, index, active, error) File "/mnt/c/Users/haray/home/tmp/siliconcompiler/siliconcompiler/siliconcompiler/core.py", line 2870, in _runtask utils.copytree(f"../../../{job}/{in_step}/{in_index}/outputs", 'inputs/', dirs_exist_ok=True, File "/mnt/c/Users/haray/home/tmp/siliconcompiler/siliconcompiler/siliconcompiler/utils.py", line 23, in copytree os.link(srcfile, dstfile) FileExistsError: [Errno 17] File exists: '../../../job0/import/0/outputs/heartbeat.sdc' -> 'inputs/heartbeat.sdc' | ERROR | job0 | syn | 0 | Uncaught exception while running step syn. | ERROR | job0 | syn | 0 | Halting step 'syn' index '0' due to errors. | ERROR | job0 | floorplan | 0 | Halting step due to previous error in syn0 | ERROR | job0 | floorplan | 0 | Halting step 'floorplan' index '0' due to errors. | ERROR | job0 | physyn | 0 | Halting step due to previous error in floorplan0 | ERROR | job0 | physyn | 0 | Halting step 'physyn' index '0' due to errors. | ERROR | job0 | place | 0 | Halting step due to previous error in physyn0 | ERROR | job0 | place | 0 | Halting step 'place' index '0' due to errors. | ERROR | job0 | cts | 0 | Halting step due to previous error in place0 | ERROR | job0 | cts | 0 | Halting step 'cts' index '0' due to errors. | ERROR | job0 | route | 0 | Halting step due to previous error in cts0 | ERROR | job0 | route | 0 | Halting step 'route' index '0' due to errors. | ERROR | job0 | dfm | 0 | Halting step due to previous error in route0 | ERROR | job0 | dfm | 0 | Halting step 'dfm' index '0' due to errors. | ERROR | job0 | export | 0 | Halting step due to previous error in dfm0 | ERROR | job0 | export | 0 | Halting step 'export' index '0' due to errors. | ERROR | job0 | --- | - | Run() failed, exiting! See previous errors.
asicflow_freepdk45 を freepdk45 に変更すると、下記のようにエラーは無くなります。
python heartbeat.py | INFO | job0 | --- | - | Loading target 'freepdk45' | INFO | job0 | --- | - | Loading function 'setup_pdk' from module 'freepdk45' | INFO | job0 | --- | - | Operating in 'asic' mode | INFO | job0 | syn | 0 | Waiting for inputs... | INFO | job0 | import | 0 | Waiting for inputs... | INFO | job0 | import | 0 | Collecting input sources | INFO | job0 | import | 0 | Copying /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v to 'inputs' directory | INFO | job0 | import | 0 | Copying /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.sdc to 'inputs' directory | INFO | job0 | import | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/import/0/sc_manifest.tcl | INFO | job0 | import | 0 | Running in /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/import/0 | INFO | job0 | import | 0 | surelog -parse /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v -top heartbeat +libext+.sv [INF:CM0023] Creating log file ./slpp_all/surelog.log. [WRN:PA0205] /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v:1: No timescale set for "heartbeat". [INF:CP0300] Compilation... [INF:CP0303] /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v:1: Compile module "work@heartbeat". [INF:CP0302] builtin.sv:4: Compile class "work@mailbox". [INF:CP0302] builtin.sv:33: Compile class "work@process". [INF:CP0302] builtin.sv:58: Compile class "work@semaphore". [INF:EL0526] Design Elaboration... [NTE:EL0503] /mnt/c/Users/haray/home/tmp/siliconcompiler/heartbeat.v:1: Top level module "work@heartbeat". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 1. [NTE:EL0510] Nb instances: 1. [NTE:EL0511] Nb leaf instances: 0. [INF:UH0706] Creating UHDM Model... [INF:UH0708] Writing UHDM DB: ./slpp_all//surelog.uhdm... [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 1 [ NOTE] : 5 | INFO | job0 | import | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/import/0/outputs/heartbeat.pkg.json | INFO | job0 | syn | 0 | Writing manifest to /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/syn/0/sc_manifest.tcl | INFO | job0 | syn | 0 | Running in /mnt/c/Users/haray/home/tmp/siliconcompiler/build/heartbeat/job0/syn/0 | INFO | job0 | syn | 0 | yosys -c /mnt/c/Users/haray/home/tmp/siliconcompiler/siliconcompiler/siliconcompiler/tools/yosys/sc_syn.tcl /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9 (git sha1 1979e0b) echo on yosys> read_verilog -sv inputs/heartbeat.v 1. Executing Verilog-2005 frontend: inputs/heartbeat.v Parsing SystemVerilog input from `inputs/heartbeat.v' to AST representation. Generating RTLIL representation for module `\heartbeat'. Successfully finished Verilog frontend. yosys> chparam -list heartbeat: N yosys> read_liberty -lib /mnt/c/Users/haray/home/tmp/siliconcompiler/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib 2. Executing Liberty frontend. Imported 134 cell types from liberty file.
demo
SiliconCompilerのデモが、
っぽい。
おわりに
どうやら、siliconcompiler.com にアカウントを作らないと、使えないっぽい。。。
