はじめに
前回は、フロアプラン (floorplan) から クロックツリー (cts) を見ました。今回は、配置 (route)です。
配置 (route)
ここからは、配置 (route) です。
| INFO | job0 | route | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/route/0/sc_manifest.tcl | INFO | job0 | route | 0 | Running in /XXXXX/build/heartbeat/job0/route/0 | INFO | job0 | route | 0 | openroad -no_init -exit /XXXXX/siliconcompiler/tools/openroad/sc_apr.tcl OpenROAD 1 v2.0-880-gd1c7001ad This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef [INFO ODB-0223] Created 22 technology layers [INFO ODB-0224] Created 27 technology vias [INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef [INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef [INFO ODB-0127] Reading DEF file: inputs/heartbeat.def [INFO ODB-0128] Design: heartbeat [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 65 components and 235 component-terminals. [INFO ODB-0133] Created 40 nets and 105 connections. [INFO ODB-0134] Finished DEF file: inputs/heartbeat.def [INFO DPL-0001] Placed 174 filler instances. [WARNING GRT-0147] Argument -overflow_iterations is deprecated. Use -congestion_iterations. [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% [INFO GRT-0023] Grid origin: (0, 0) [WARNING GRT-0043] No OR_DEFAULT vias defined. [INFO GRT-0224] Chose via via1_4 as default. [INFO GRT-0224] Chose via via2_8 as default. [INFO GRT-0224] Chose via via3_2 as default. [INFO GRT-0224] Chose via via4_0 as default. [INFO GRT-0224] Chose via via5_0 as default. [INFO GRT-0224] Chose via via6_0 as default. [INFO GRT-0224] Chose via via7_0 as default. [INFO GRT-0224] Chose via via8_0 as default. [INFO GRT-0224] Chose via via9_0 as default. [INFO GRT-0088] Layer metal1 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1350 [INFO GRT-0088] Layer metal2 Track-Pitch = 0.1900 line-2-Via Pitch: 0.1400 [INFO GRT-0088] Layer metal3 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1400 [INFO GRT-0088] Layer metal4 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal5 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal6 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800 [INFO GRT-0088] Layer metal7 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000 [INFO GRT-0088] Layer metal8 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000 [INFO GRT-0088] Layer metal9 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000 [INFO GRT-0088] Layer metal10 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000 [INFO GRT-0003] Macros: 0 [INFO GRT-0004] Blockages: 314 [INFO GRT-0019] Found 4 clock nets. [INFO GRT-0001] Minimum degree: 2 [INFO GRT-0002] Maximum degree: 10 [INFO GRT-0017] Processing 1238 blockages on layer metal1. [INFO GRT-0053] Routing resources analysis: Routing Original Derated Resource Layer Direction Resources Resources Reduction (%) --------------------------------------------------------------- metal1 Horizontal 2940 260 91.16% metal2 Vertical 2156 520 75.88% metal3 Horizontal 2940 949 67.72% metal4 Vertical 1372 806 41.25% metal5 Horizontal 1372 806 41.25% metal6 Vertical 1372 806 41.25% metal7 Horizontal 392 195 50.26% metal8 Vertical 392 195 50.26% metal9 Horizontal 196 0 100.00% metal10 Vertical 196 0 100.00% --------------------------------------------------------------- [INFO GRT-0191] Wirelength: 127, Wirelength1: 0 [INFO GRT-0192] Number of segments: 65 [INFO GRT-0193] Number of shifts: 0 [INFO GRT-0097] First L Route. [INFO GRT-0191] Wirelength: 127, Wirelength1: 127 [INFO GRT-0192] Number of segments: 65 [INFO GRT-0193] Number of shifts: 0 [INFO GRT-0135] Overflow report. [INFO GRT-0136] Total hCap : 2210 [INFO GRT-0137] Total vCap : 2327 [INFO GRT-0138] Total usage : 127 [INFO GRT-0139] Max H overflow : 0 [INFO GRT-0140] Max V overflow : 0 [INFO GRT-0141] Max overflow : 0 [INFO GRT-0142] Number of overflow edges : 0 [INFO GRT-0143] H overflow : 0 [INFO GRT-0144] V overflow : 0 [INFO GRT-0145] Final overflow : 0 [INFO GRT-0098] Second L Route. [INFO GRT-0135] Overflow report. [INFO GRT-0136] Total hCap : 2210 [INFO GRT-0137] Total vCap : 2327 [INFO GRT-0138] Total usage : 127 [INFO GRT-0139] Max H overflow : 0 [INFO GRT-0140] Max V overflow : 0 [INFO GRT-0141] Max overflow : 0 [INFO GRT-0142] Number of overflow edges : 0 [INFO GRT-0143] H overflow : 0 [INFO GRT-0144] V overflow : 0 [INFO GRT-0145] Final overflow : 0 [INFO GRT-0099] First Z Route. [INFO GRT-0135] Overflow report. [INFO GRT-0136] Total hCap : 2210 [INFO GRT-0137] Total vCap : 2327 [INFO GRT-0138] Total usage : 127 [INFO GRT-0139] Max H overflow : 0 [INFO GRT-0140] Max V overflow : 0 [INFO GRT-0141] Max overflow : 0 [INFO GRT-0142] Number of overflow edges : 0 [INFO GRT-0143] H overflow : 0 [INFO GRT-0144] V overflow : 0 [INFO GRT-0145] Final overflow : 0 [INFO GRT-0100] LV routing round 0, enlarge 10. [INFO GRT-0182] 10 threshold, 10 expand. [INFO GRT-0126] Overflow report: [INFO GRT-0127] Total usage : 127 [INFO GRT-0128] Max H overflow : 0 [INFO GRT-0129] Max V overflow : 0 [INFO GRT-0130] Max overflow : 0 [INFO GRT-0131] Number overflow edges: 0 [INFO GRT-0132] H overflow : 0 [INFO GRT-0133] V overflow : 0 [INFO GRT-0134] Final overflow : 0 [INFO GRT-0100] LV routing round 1, enlarge 15. [INFO GRT-0182] 5 threshold, 15 expand. [INFO GRT-0126] Overflow report: [INFO GRT-0127] Total usage : 127 [INFO GRT-0128] Max H overflow : 0 [INFO GRT-0129] Max V overflow : 0 [INFO GRT-0130] Max overflow : 0 [INFO GRT-0131] Number overflow edges: 0 [INFO GRT-0132] H overflow : 0 [INFO GRT-0133] V overflow : 0 [INFO GRT-0134] Final overflow : 0 [INFO GRT-0100] LV routing round 2, enlarge 20. [INFO GRT-0182] 1 threshold, 20 expand. [INFO GRT-0126] Overflow report: [INFO GRT-0127] Total usage : 127 [INFO GRT-0128] Max H overflow : 0 [INFO GRT-0129] Max V overflow : 0 [INFO GRT-0130] Max overflow : 0 [INFO GRT-0131] Number overflow edges: 0 [INFO GRT-0132] H overflow : 0 [INFO GRT-0133] V overflow : 0 [INFO GRT-0134] Final overflow : 0 Usage checked [INFO GRT-0105] Maze routing finished. Final 2D results: [INFO GRT-0126] Overflow report: [INFO GRT-0127] Total usage : 127 [INFO GRT-0128] Max H overflow : 0 [INFO GRT-0129] Max V overflow : 0 [INFO GRT-0130] Max overflow : 0 [INFO GRT-0131] Number overflow edges: 0 [INFO GRT-0132] H overflow : 0 [INFO GRT-0133] V overflow : 0 [INFO GRT-0134] Final overflow : 0 [INFO GRT-0106] Layer assignment begins. [INFO GRT-0107] Layer assignment finished. [INFO GRT-0108] Post-processing begins. [INFO GRT-0109] Post-processing finished. Starting via filling. [INFO GRT-0197] Via related to pin nodes: 169 [INFO GRT-0198] Via related Steiner nodes: 1 [INFO GRT-0199] Via filling finished. [INFO GRT-0111] Final number of vias: 191 [INFO GRT-0112] Final usage 3D: 702 [WARNING GRT-0211] dbGcellGrid already exists in db. Clearing existing dbGCellGrid. [INFO GRT-0096] Final congestion report: Layer Resource Demand Usage (%) Max H / Max V / Total Overflow --------------------------------------------------------------------------------------- metal1 260 0 0.00% 0 / 0 / 0 metal2 520 44 8.46% 0 / 0 / 0 metal3 949 66 6.95% 0 / 0 / 0 metal4 806 19 2.36% 0 / 0 / 0 metal5 806 0 0.00% 0 / 0 / 0 metal6 806 0 0.00% 0 / 0 / 0 metal7 195 0 0.00% 0 / 0 / 0 metal8 195 0 0.00% 0 / 0 / 0 metal9 0 0 0.00% 0 / 0 / 0 metal10 0 0 0.00% 0 / 0 / 0 --------------------------------------------------------------------------------------- Total 4537 129 2.84% 0 / 0 / 0 [INFO GRT-0018] Total wirelength: 459 um [INFO GRT-0014] Routed nets: 32 [INFO ANT-0001] Found 0 pin violations. [INFO ANT-0002] Found 0 net violations in 40 nets. [INFO ORD-0030] Using 8 thread(s). [INFO DRT-0149] Reading tech and libs. Units: 2000 Number of layers: 21 Number of macros: 134 Number of vias: 27 Number of viarulegen: 19 [INFO DRT-0150] Reading design. Design: heartbeat Die area: ( 0 0 ) ( 60800 60800 ) Number of track patterns: 20 Number of DEF vias: 0 Number of components: 239 Number of terminals: 3 Number of snets: 0 Number of nets: 40 [INFO DRT-0151] Reading guide. Number of guides: 265 [INFO DRT-0167] List of default vias: Layer via1 default via: via1_7 Layer via2 default via: via2_5 Layer via3 default via: via3_2 Layer via4 default via: via4_0 Layer via5 default via: via5_0 Layer via6 default via: via6_0 Layer via7 default via: via7_0 Layer via8 default via: via8_0 Layer via9 default via: via9_0 [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. [INFO DRT-0164] Number of unique instances = 27. [INFO DRT-0168] Init region query. [INFO DRT-0024] Complete FR_MASTERSLICE. [INFO DRT-0024] Complete FR_VIA. [INFO DRT-0024] Complete metal1. [INFO DRT-0024] Complete via1. [INFO DRT-0024] Complete metal2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete metal3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete metal4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete metal5. [INFO DRT-0024] Complete via5. [INFO DRT-0024] Complete metal6. [INFO DRT-0024] Complete via6. [INFO DRT-0024] Complete metal7. [INFO DRT-0024] Complete via7. [INFO DRT-0024] Complete metal8. [INFO DRT-0024] Complete via8. [INFO DRT-0024] Complete metal9. [INFO DRT-0024] Complete via9. [INFO DRT-0024] Complete metal10. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] FR_VIA shape region query size = 0. [INFO DRT-0033] metal1 shape region query size = 1238. [INFO DRT-0033] via1 shape region query size = 0. [INFO DRT-0033] metal2 shape region query size = 2. [INFO DRT-0033] via2 shape region query size = 0. [INFO DRT-0033] metal3 shape region query size = 1. [INFO DRT-0033] via3 shape region query size = 0. [INFO DRT-0033] metal4 shape region query size = 0. [INFO DRT-0033] via4 shape region query size = 0. [INFO DRT-0033] metal5 shape region query size = 0. [INFO DRT-0033] via5 shape region query size = 0. [INFO DRT-0033] metal6 shape region query size = 0. [INFO DRT-0033] via6 shape region query size = 0. [INFO DRT-0033] metal7 shape region query size = 0. [INFO DRT-0033] via7 shape region query size = 0. [INFO DRT-0033] metal8 shape region query size = 0. [INFO DRT-0033] via8 shape region query size = 0. [INFO DRT-0033] metal9 shape region query size = 0. [INFO DRT-0033] via9 shape region query size = 0. [INFO DRT-0033] metal10 shape region query size = 0. [INFO DRT-0165] Start pin access. [INFO DRT-0078] Complete 49 pins. [INFO DRT-0081] Complete 15 unique inst patterns. [INFO DRT-0084] Complete 29 groups. #scanned instances = 239 #unique instances = 27 #stdCellGenAp = 328 #stdCellValidPlanarAp = 0 #stdCellValidViaAp = 271 #stdCellPinNoAp = 0 #stdCellPinCnt = 105 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 [INFO DRT-0166] Complete pin access. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 97.61 (MB), peak = 171.71 (MB) [INFO DRT-0169] Post process guides. [INFO DRT-0176] GCELLGRID X 0 DO 14 STEP 4200 ; [INFO DRT-0177] GCELLGRID Y 0 DO 14 STEP 4200 ; [INFO DRT-0028] Complete FR_MASTERSLICE. [INFO DRT-0028] Complete FR_VIA. [INFO DRT-0028] Complete metal1. [INFO DRT-0028] Complete via1. [INFO DRT-0028] Complete metal2. [INFO DRT-0028] Complete via2. [INFO DRT-0028] Complete metal3. [INFO DRT-0028] Complete via3. [INFO DRT-0028] Complete metal4. [INFO DRT-0028] Complete via4. [INFO DRT-0028] Complete metal5. [INFO DRT-0028] Complete via5. [INFO DRT-0028] Complete metal6. [INFO DRT-0028] Complete via6. [INFO DRT-0028] Complete metal7. [INFO DRT-0028] Complete via7. [INFO DRT-0028] Complete metal8. [INFO DRT-0028] Complete via8. [INFO DRT-0028] Complete metal9. [INFO DRT-0028] Complete via9. [INFO DRT-0028] Complete metal10. [INFO DRT-0178] Init guide query. [INFO DRT-0035] Complete FR_MASTERSLICE (guide). [INFO DRT-0035] Complete FR_VIA (guide). [INFO DRT-0035] Complete metal1 (guide). [INFO DRT-0035] Complete via1 (guide). [INFO DRT-0035] Complete metal2 (guide). [INFO DRT-0035] Complete via2 (guide). [INFO DRT-0035] Complete metal3 (guide). [INFO DRT-0035] Complete via3 (guide). [INFO DRT-0035] Complete metal4 (guide). [INFO DRT-0035] Complete via4 (guide). [INFO DRT-0035] Complete metal5 (guide). [INFO DRT-0035] Complete via5 (guide). [INFO DRT-0035] Complete metal6 (guide). [INFO DRT-0035] Complete via6 (guide). [INFO DRT-0035] Complete metal7 (guide). [INFO DRT-0035] Complete via7 (guide). [INFO DRT-0035] Complete metal8 (guide). [INFO DRT-0035] Complete via8 (guide). [INFO DRT-0035] Complete metal9 (guide). [INFO DRT-0035] Complete via9 (guide). [INFO DRT-0035] Complete metal10 (guide). [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. [INFO DRT-0036] FR_VIA guide region query size = 0. [INFO DRT-0036] metal1 guide region query size = 92. [INFO DRT-0036] via1 guide region query size = 0. [INFO DRT-0036] metal2 guide region query size = 74. [INFO DRT-0036] via2 guide region query size = 0. [INFO DRT-0036] metal3 guide region query size = 45. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] metal4 guide region query size = 6. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] metal5 guide region query size = 0. [INFO DRT-0036] via5 guide region query size = 0. [INFO DRT-0036] metal6 guide region query size = 0. [INFO DRT-0036] via6 guide region query size = 0. [INFO DRT-0036] metal7 guide region query size = 0. [INFO DRT-0036] via7 guide region query size = 0. [INFO DRT-0036] metal8 guide region query size = 0. [INFO DRT-0036] via8 guide region query size = 0. [INFO DRT-0036] metal9 guide region query size = 0. [INFO DRT-0036] via9 guide region query size = 0. [INFO DRT-0036] metal10 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO DRT-0185] Post process initialize RPin region query. [INFO DRT-0181] Start track assignment. [INFO DRT-0184] Done with 80 vertical wires in 1 frboxes and 137 horizontal wires in 1 frboxes. [INFO DRT-0186] Done with 9 vertical wires in 1 frboxes and 22 horizontal wires in 1 frboxes. [INFO DRT-0182] Complete track assignment. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 98.35 (MB), peak = 171.71 (MB) [INFO DRT-0187] Start routing data preparation. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 98.35 (MB), peak = 171.71 (MB) [INFO DRT-0194] Start detail routing. [INFO DRT-0195] Start 0th optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 101.29 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 104.96 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 106.55 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 106.55 (MB). [INFO DRT-0199] Number of violations = 12. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 658.96 (MB), peak = 658.96 (MB) Total wire length = 264 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 108 um. Total wire length on LAYER metal3 = 132 um. Total wire length on LAYER metal4 = 22 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 198. Up-via summary (total 198):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 9 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 198 [INFO DRT-0195] Start 1st optimization iteration. Completing 10% with 12 violations. elapsed time = 00:00:00, memory = 659.97 (MB). Completing 20% with 12 violations. elapsed time = 00:00:00, memory = 659.97 (MB). Completing 30% with 12 violations. elapsed time = 00:00:00, memory = 659.97 (MB). Completing 40% with 12 violations. elapsed time = 00:00:00, memory = 659.97 (MB). Completing 50% with 12 violations. elapsed time = 00:00:00, memory = 663.59 (MB). Completing 60% with 12 violations. elapsed time = 00:00:00, memory = 663.59 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 664.62 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 664.62 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 2nd optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 17th optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 25th optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 33rd optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 41st optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 49th optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0195] Start 57th optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 20% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 30% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 40% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 50% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 60% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 70% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 80% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 90% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). Completing 100% with 0 violations. elapsed time = 00:00:00, memory = 670.04 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0198] Complete detail routing. Total wire length = 261 um. Total wire length on LAYER metal1 = 1 um. Total wire length on LAYER metal2 = 109 um. Total wire length on LAYER metal3 = 130 um. Total wire length on LAYER metal4 = 19 um. Total wire length on LAYER metal5 = 0 um. Total wire length on LAYER metal6 = 0 um. Total wire length on LAYER metal7 = 0 um. Total wire length on LAYER metal8 = 0 um. Total wire length on LAYER metal9 = 0 um. Total wire length on LAYER metal10 = 0 um. Total number of vias = 196. Up-via summary (total 196):. ---------------------- FR_MASTERSLICE 0 metal1 99 metal2 90 metal3 7 metal4 0 metal5 0 metal6 0 metal7 0 metal8 0 metal9 0 ---------------------- 196 [INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:00, memory = 670.04 (MB), peak = 670.04 (MB) [INFO DRT-0180] Post processing. SC_METRIC: report_checks -path_delay max | INFO | job0 | route | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/route /0/outputs/heartbeat.pkg.json Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Cap Delay Time Description ---------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 5.06 0.00 0.00 ^ clk (in) 7.65 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 4.83 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4) 0.00 0.04 ^ _72_/CK (DFFR_X1) 7.54 0.12 0.15 ^ _72_/Q (DFFR_X1) 8.73 0.08 0.23 ^ _43_/ZN (AND4_X1) 4.81 0.05 0.28 v _46_/ZN (NAND4_X1) 1.31 0.05 0.32 v _54_/ZN (XNOR2_X1) 0.00 0.32 v _79_/D (DFFR_X1) 0.32 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 5.06 0.00 1.00 ^ clk (in) 7.65 0.02 1.02 ^ clkbuf_0_clk/Z (BUF_X4) 5.75 0.02 1.04 ^ clkbuf_1_1__f_clk/Z (BUF_X4) 0.00 1.04 ^ _79_/CK (DFFR_X1) 0.00 1.04 clock reconvergence pessimism -0.04 1.00 library setup time 1.00 data required time ---------------------------------------------------------------- 1.00 data required time -0.32 data arrival time ---------------------------------------------------------------- 0.67 slack (MET) SC_METRIC: report_checks -path_delay min Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _72_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Cap Delay Time Description ---------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 5.06 0.00 0.00 ^ clk (in) 7.65 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 4.83 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4) 0.00 0.04 ^ _72_/CK (DFFR_X1) 1.69 0.07 0.11 ^ _72_/QN (DFFR_X1) 0.00 0.11 ^ _72_/D (DFFR_X1) 0.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 5.06 0.00 0.00 ^ clk (in) 7.65 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 4.83 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4) 0.00 0.04 ^ _72_/CK (DFFR_X1) 0.00 0.04 clock reconvergence pessimism 0.01 0.05 library hold time 0.05 data required time ---------------------------------------------------------------- 0.05 data required time -0.11 data arrival time ---------------------------------------------------------------- 0.06 slack (MET) SC_METRIC: unconstrained Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Cap Delay Time Description ---------------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock source latency 5.06 0.00 0.00 ^ clk (in) 7.65 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 4.83 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4) 0.00 0.04 ^ _72_/CK (DFFR_X1) 7.54 0.12 0.15 ^ _72_/Q (DFFR_X1) 8.73 0.08 0.23 ^ _43_/ZN (AND4_X1) 4.81 0.05 0.28 v _46_/ZN (NAND4_X1) 1.31 0.05 0.32 v _54_/ZN (XNOR2_X1) 0.00 0.32 v _79_/D (DFFR_X1) 0.32 data arrival time 1.00 1.00 clock clk (rise edge) 0.00 1.00 clock source latency 5.06 0.00 1.00 ^ clk (in) 7.65 0.02 1.02 ^ clkbuf_0_clk/Z (BUF_X4) 5.75 0.02 1.04 ^ clkbuf_1_1__f_clk/Z (BUF_X4) 0.00 1.04 ^ _79_/CK (DFFR_X1) 0.00 1.04 clock reconvergence pessimism -0.04 1.00 library setup time 1.00 data required time ---------------------------------------------------------------- 1.00 data required time -0.32 data arrival time ---------------------------------------------------------------- 0.67 slack (MET) SC_METRIC: wns wns 0.00 SC_METRIC: tns tns 0.00 SC_METRIC: setupslack worst slack 0.67 SC_METRIC: holdslack worst slack 0.06 SC_METRIC: power Group Internal Switching Leakage Total Power Power Power Power ---------------------------------------------------------------- Sequential 3.84e-05 1.38e-06 5.82e-07 4.04e-05 35.1% Combinational 5.11e-05 2.26e-05 7.29e-07 7.45e-05 64.9% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- Total 8.95e-05 2.40e-05 1.31e-06 1.15e-04 100.0% 77.9% 20.9% 1.1% SC_METRIC: cellarea Design area 74 u^2 11% utilization.
ざっくりな消費電力も出てきますね。
| INFO | job0 | route | 0 | Writing manifest to /XXX/build/heartbeat/job0/route/0/outputs/heartbeat.pkg.json
配線後のデータは、json フォーマットのファイルにストアされています。
おわりに
今回は、配置 (route) を見てみました。次回は、dfm です。