はじめに
前回は、配置 (route) を見てみました。今回は、Design For Manufacturing (dfm) です。
Design For Manufacturing (dfm)
ここからは、Design For Manufacturing (dfm) です。
| INFO | job0 | dfm | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/dfm/0/sc_manifest.tcl
| INFO | job0 | dfm | 0 | Running in /XXXXX/build/heartbeat/job0/dfm/0
| INFO | job0 | dfm | 0 | openroad -no_init -exit /XXXX/siliconcompiler/tools/openroad/sc_apr.tcl
| INFO | job0 | dfm | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/dfm/0/outputs/heartbeat.pkg.json
OpenROAD 1 v2.0-880-gd1c7001ad
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0223] Created 22 technology layers
[INFO ODB-0224] Created 27 technology vias
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225] Created 134 library cells
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0127] Reading DEF file: inputs/heartbeat.def
[INFO ODB-0128] Design: heartbeat
[INFO ODB-0131] Created 239 components and 583 component-terminals.
[INFO ODB-0133] Created 40 nets and 105 connections.
[INFO ODB-0134] Finished DEF file: inputs/heartbeat.def
SC_METRIC: report_checks -path_delay max
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.71 0.00 0.00 ^ clk (in)
7.50 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4)
5.54 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4)
0.00 0.04 ^ _72_/CK (DFFR_X1)
8.19 0.12 0.15 ^ _72_/Q (DFFR_X1)
8.97 0.08 0.24 ^ _43_/ZN (AND4_X1)
4.63 0.04 0.28 v _46_/ZN (NAND4_X1)
1.36 0.05 0.33 v _54_/ZN (XNOR2_X1)
0.00 0.33 v _79_/D (DFFR_X1)
0.33 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock source latency
3.71 0.00 1.00 ^ clk (in)
7.50 0.02 1.02 ^ clkbuf_0_clk/Z (BUF_X4)
7.00 0.02 1.04 ^ clkbuf_1_1__f_clk/Z (BUF_X4)
0.00 1.04 ^ _79_/CK (DFFR_X1)
0.00 1.04 clock reconvergence pessimism
-0.04 1.00 library setup time
1.00 data required time
----------------------------------------------------------------
1.00 data required time
-0.33 data arrival time
----------------------------------------------------------------
0.67 slack (MET)
SC_METRIC: report_checks -path_delay min
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
ndpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.71 0.00 0.00 ^ clk (in)
7.50 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4)
5.54 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4)
0.00 0.04 ^ _72_/CK (DFFR_X1)
1.44 0.07 0.10 ^ _72_/QN (DFFR_X1)
0.00 0.10 ^ _72_/D (DFFR_X1)
0.10 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.71 0.00 0.00 ^ clk (in)
7.50 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4)
5.54 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4)
0.00 0.04 ^ _72_/CK (DFFR_X1)
0.00 0.04 clock reconvergence pessimism
0.01 0.04 library hold time
0.04 data required time
----------------------------------------------------------------
0.04 data required time
-0.10 data arrival time
----------------------------------------------------------------
0.06 slack (MET)
SC_METRIC: unconstrained
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.71 0.00 0.00 ^ clk (in)
7.50 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4)
5.54 0.02 0.04 ^ clkbuf_1_0__f_clk/Z (BUF_X4)
0.00 0.04 ^ _72_/CK (DFFR_X1)
8.19 0.12 0.15 ^ _72_/Q (DFFR_X1)
8.97 0.08 0.24 ^ _43_/ZN (AND4_X1)
4.63 0.04 0.28 v _46_/ZN (NAND4_X1)
1.36 0.05 0.33 v _54_/ZN (XNOR2_X1)
0.00 0.33 v _79_/D (DFFR_X1)
0.33 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock source latency
3.71 0.00 1.00 ^ clk (in)
7.50 0.02 1.02 ^ clkbuf_0_clk/Z (BUF_X4)
7.00 0.02 1.04 ^ clkbuf_1_1__f_clk/Z (BUF_X4)
0.00 1.04 ^ _79_/CK (DFFR_X1)
0.00 1.04 clock reconvergence pessimism
-0.04 1.00 library setup time
1.00 data required time
----------------------------------------------------------------
1.00 data required time
-0.33 data arrival time
----------------------------------------------------------------
0.67 slack (MET)
SC_METRIC: wns
wns 0.00
SC_METRIC: tns
tns 0.00
SC_METRIC: setupslack
worst slack 0.67
SC_METRIC: holdslack
worst slack 0.06
SC_METRIC: power
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 3.84e-05 1.46e-06 5.82e-07 4.04e-05 34.4%
Combinational 5.15e-05 2.48e-05 7.29e-07 7.70e-05 65.6%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 8.99e-05 2.63e-05 1.31e-06 1.17e-04 100.0%
76.5% 22.4% 1.1%
SC_METRIC: cellarea
Design area 74 u^2 11% utilization.
export
ここからは、export です。これが終了すると、Klayout にて、配置配線の結果が表示されます。
| INFO | job0 | export | 0 | Writing manifest to /XXXXX/build/hearbeat/job0/export/0/sc_manifest.tcl | INFO | job0 | export | 0 | Running in /XXXXX/build/heartbeat/job0/export/0 | INFO | job0 | export | 0 | klayout -zz /XXXXX/siliconcompiler/tools/klayout/klayout_export.py -rd design_name=heartbeat -rd in_def=inputs/heartbeat.def -rd seal_file= -rd in_files=/XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/gds/NangateOpenCellLibrary.gds -rd out_file=outputs/heartbeat.gds -rd tech_file=/XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/setup/klayout/freepdk45.lyt -rd foundry_lefs=/XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef -rd macro_lefs= -rd config_file= -r klayout_export.py | INFO | job0 | export | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/export/0/outputs/heartbeat.pkg.json
export/0/outputs/heartbeat.pkg.json が最終成果物？
[INFO] Clearing cells...
[INFO] Merging GDS/OAS files...
/XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/gds/NangateOpenCellLibrary.gds
[INFO] Copying toplevel cell 'heartbeat'
WARNING: no fill config file specified
[INFO] Checking for missing GDS/OAS...
[INFO] All LEF cells have matching GDS/OAS cells
[INFO] Writing out GDS/OAS 'outputs/heartbeat.gds'
outputs/heartbeat.gds が Klayout の入力データ？
| INFO | job0 | --- | - | Showing file None
| INFO | job0 | --- | - | Writing manifest to /XXXX/build/_show/sc_manifest.tcl
| INFO | job0 | --- | - | Writing manifest to /XXXXX/build/_show/sc_manifest.json
---------------------------------------------------------------------------------------------------------------------------------------
SUMMARY:
design : heartbeat
params : None
jobdir : /XXXXX/build/heartbeat/job0
foundry : virtual
process : freepdk45
targetlibs : NangateOpenCellLibrary
import0 syn0 floorplan0 physyn0 place0 cts0 route0 dfm0 export0
errors 0 0 0 0 0 0 0 0 0
warnings 0 72 1 0 2 4 3 0 0
drvs 0 0 0 0 0 0 0 0 0
unconstrained 0 0 0 0 0 0 0 0 0
coverage 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
security 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
luts 0 0 0 0 0 0 0 0 0
dsps 0 0 0 0 0 0 0 0 0
brams 0 0 0 0 0 0 0 0 0
cellarea 0.0 67.03 67.0 67.0 69.0 74.0 74.0 74.0 0.0
totalarea 0.0 0.0 670.0 670.0 690.0 672.73 672.73 672.73 0.0
utilization 0.0 0.0 10.0 10.0 10.0 11.0 11.0 11.0 0.0
peakpower 0.0 0.0 4.24e-05 4.24e-05 4.23e-05 0.000111 0.000115 0.000117 0.0
standbypower 0.0 0.0 9.88e-07 9.88e-07 1.05e-06 1.31e-06 1.31e-06 1.31e-06 0.0
irdrop 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
holdslack 0.0 0.0 0.06 0.06 0.06 0.06 0.06 0.06 0.0
holdwns 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
holdtns 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
holdpaths 0 0 0 0 0 0 0 0 0
setupslack 0.0 0.0 0.67 0.67 0.68 0.68 0.67 0.67 0.0
setupwns 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
setuptns 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
setuppaths 0 0 0 0 0 0 0 0 0
cells 0 24 60 60 62 65 239 239 0
registers 0 0 0 0 0 0 0 0 0
buffers 0 0 0 0 0 0 0 0 0
transistors 0 0 0 0 0 0 0 0 0
nets 0 0 35 35 37 40 40 40 0
pins 0 0 3 3 3 3 3 3 0
vias 0 0 0 0 0 0 196 0 0
wirelength 0.0 0.0 0.0 0.0 0.0 0.0 261.0 0.0 0.0
overflow 0 0 0 0 0 0 0 0 0
runtime 0.5 1.45 1.95 1.62 1.84 3.07 2.89 1.83 1.45
memory 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
memory 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
---------------------------------------------------------------------------------------------------------------------------------------
各種情報？
Klayout
| INFO | job0 | --- | - | Showing file None | INFO | job0 | --- | - | Writing manifest to /XXXXX/build/_show/sc_manifest.tcl | INFO | job0 | --- | - | Writing manifest to /XXXXX/build/_show/sc_manifest.json
最後に、Klayout にて生成されたレイアウトが表示されました。
おわりに
4回にわたって、SiliconCompiler のサンプルコードの実行ログを眺めてみました。
ログは長かったですね。。。
