はじめに
前回は、論理合成までを見ました。今回は、フロアプランの部分を見ていきます。
openROADにて、フロアプラン (floorplan)
ここからは、openROADにて、フロアプラン (floorplan)です。
| INFO | job0 | floorplan | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/floorplan/0/sc_manifest.tcl
| INFO | job0 | floorplan | 0 | Running in /XXXXX/build/heartbeat/job0/floorplan/0
| INFO | job0 | floorplan | 0 | openroad -no_init -exit /XXXXX/siliconcompiler/tools/openroad/sc_apr.tcl
| INFO | job0 | floorplan | 0 | Writing manifest to /XXXXX/siliconcompiler/build/hearbeat/job0/floorplan/0/outputs/heartbeat.pkg.json
OpenROAD 1 v2.0-880-gd1c7001ad
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0223] Created 22 technology layers
[INFO ODB-0224] Created 27 technology vias
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.l
ef
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225] Created 134 library cells
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
(0, 0) (30.4, 30.4)
(1.9, 1.9) (28.499999999999996, 28.499999999999996)
0 0 30.4 30.4
1.9 1.9 28.499999999999996 28.499999999999996
[INFO IFP-0001] Added 18 rows of 140 sites.
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
[WARNING TAP-0014] endcap_cpp option is deprecated.
[INFO TAP-0001] Found 0 macro blocks.
[INFO TAP-0002] Original rows: 18
[INFO TAP-0003] Created 0 rows for a total of 18 rows.
[INFO TAP-0004] Inserted 36 endcaps.
[INFO TAP-0005] Inserted 0 tapcells.
[INFO RSZ-0026] Removed 16 buffers.
SC_METRIC: report_checks -path_delay max
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
8.19 0.11 0.11 ^ _72_/Q (DFFR_X1)
8.97 0.08 0.20 ^ _43_/ZN (AND4_X1)
4.63 0.04 0.24 v _46_/ZN (NAND4_X1)
1.36 0.05 0.29 v _54_/ZN (XNOR2_X1)
0.00 0.29 v _79_/D (DFFR_X1)
0.29 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ _79_/CK (DFFR_X1)
-0.04 0.96 library setup time
0.96 data required time
----------------------------------------------------------------
0.96 data required time
-0.29 data arrival time
----------------------------------------------------------------
0.67 slack (MET)
SC_METRIC: report_checks -path_delay min
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
1.44 0.06 0.06 ^ _72_/QN (DFFR_X1)
0.00 0.06 ^ _72_/D (DFFR_X1)
0.06 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _72_/CK (DFFR_X1)
0.01 0.01 library hold time
0.01 data required time
----------------------------------------------------------------
0.01 data required time
-0.06 data arrival time
----------------------------------------------------------------
0.06 slack (MET)
SC_METRIC: unconstrained
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
8.19 0.11 0.11 ^ _72_/Q (DFFR_X1)
8.97 0.08 0.20 ^ _43_/ZN (AND4_X1)
4.63 0.04 0.24 v _46_/ZN (NAND4_X1)
1.36 0.05 0.29 v _54_/ZN (XNOR2_X1)
0.00 0.29 v _79_/D (DFFR_X1)
0.29 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ _79_/CK (DFFR_X1)
-0.04 0.96 library setup time
0.96 data required time
----------------------------------------------------------------
0.96 data required time
-0.29 data arrival time
----------------------------------------------------------------
0.67 slack (MET)
SC_METRIC: wns
wns 0.00
SC_METRIC: tns
tns 0.00
SC_METRIC: setupslack
worst slack 0.67
SC_METRIC: holdslack
worst slack 0.06
SC_METRIC: power
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 3.87e-05 1.46e-06 5.82e-07 4.07e-05 95.9%
Combinational 7.60e-07 5.70e-07 4.06e-07 1.74e-06 4.1%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.94e-05 2.03e-06 9.88e-07 4.24e-05 100.0%
92.9% 4.8% 2.3%
SC_METRIC: cellarea
Design area 67 u^2 10% utilization.
回路規模が小さいので、それほど情報はないですね。Design area は全体の10%のようです。
物理合成 (physyn)
ここからは物理合成(physyn)です。
| INFO | job0 | physyn | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/physyn/0/sc_manifest.tcl
| INFO | job0 | physyn | 0 | Running in /XXXXX/build/heartbeat/job0/physyn/0
| INFO | job0 | physyn | 0 | openroad -no_init -exit /XXXXX/tools/openroad/sc_apr.tcl
| INFO | job0 | physyn | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/physyn/0/outputs/heartbeat.pkg.json
OpenROAD 1 v2.0-880-gd1c7001ad
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0223] Created 22 technology layers
[INFO ODB-0224] Created 27 technology vias
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225] Created 134 library cells
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0128] Design: heartbeat
[INFO ODB-0130] Created 3 pins.
[INFO ODB-0131] Created 60 components and 215 component-terminals.
[INFO ODB-0133] Created 35 nets and 95 connections.
[INFO ODB-0134] Finished DEF file: inputs/heartbeat.def
NOP
SC_METRIC: report_checks -path_delay max
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
8.19 0.11 0.11 ^ _72_/Q (DFFR_X1)
8.97 0.08 0.20 ^ _43_/ZN (AND4_X1)
4.63 0.04 0.24 v _46_/ZN (NAND4_X1)
1.36 0.05 0.29 v _54_/ZN (XNOR2_X1)
0.00 0.29 v _79_/D (DFFR_X1)
0.29 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ _79_/CK (DFFR_X1)
-0.04 0.96 library setup time
0.96 data required time
----------------------------------------------------------------
0.96 data required time
-0.29 data arrival time
----------------------------------------------------------------
0.67 slack (MET)
SC_METRIC: report_checks -path_delay min
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
1.44 0.06 0.06 ^ _72_/QN (DFFR_X1)
0.00 0.06 ^ _72_/D (DFFR_X1)
0.06 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _72_/CK (DFFR_X1)
0.01 0.01 library hold time
0.01 data required time
----------------------------------------------------------------
0.01 data required time
-0.06 data arrival time
----------------------------------------------------------------
0.06 slack (MET)
SC_METRIC: unconstrained
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
8.19 0.11 0.11 ^ _72_/Q (DFFR_X1)
8.97 0.08 0.20 ^ _43_/ZN (AND4_X1)
4.63 0.04 0.24 v _46_/ZN (NAND4_X1)
1.36 0.05 0.29 v _54_/ZN (XNOR2_X1)
0.00 0.29 v _79_/D (DFFR_X1)
0.29 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ _79_/CK (DFFR_X1)
-0.04 0.96 library setup time
0.96 data required time
----------------------------------------------------------------
0.96 data required time
-0.29 data arrival time
----------------------------------------------------------------
0.67 slack (MET)
SC_METRIC: wns
wns 0.00
SC_METRIC: tns
tns 0.00
SC_METRIC: setupslack
worst slack 0.67
SC_METRIC: holdslack
worst slack 0.06
SC_METRIC: power
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 3.87e-05 1.46e-06 5.82e-07 4.07e-05 95.9%
Combinational 7.60e-07 5.70e-07 4.06e-07 1.74e-06 4.1%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.94e-05 2.03e-06 9.88e-07 4.24e-05 100.0%
92.9% 4.8% 2.3%
SC_METRIC: cellarea
Design area 67 u^2 10% utilization.
フロアプラン(floorplan)同様に、物理合成(physyn)も回路規模が小さいので、それほど情報はないですね。Design area は全体の10%のようです。
配置 (place)
ここからは配置(oute)です。
| INFO | job0 | place | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/place/0/sc_manifest.tcl
| INFO | job0 | place | 0 | Running in /XXXXX/build/heartbeat/job0/place/0
| INFO | job0 | place | 0 | openroad -no_init -exit /XXXXX/siliconcompiler/tools/openroad/sc_apr.tcl
OpenROAD 1 v2.0-880-gd1c7001ad
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0223] Created 22 technology layers
[INFO ODB-0224] Created 27 technology vias
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef
[INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0225] Created 134 library cells
[INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef
[INFO ODB-0127] Reading DEF file: inputs/heartbeat.def
[INFO ODB-0128] Design: heartbeat
[INFO ODB-0130] Created 3 pins.
[INFO ODB-0131] Created 60 components and 215 component-terminals.
[INFO ODB-0133] Created 35 nets and 95 connections.
[INFO ODB-0134] Finished DEF file: inputs/heartbeat.def
[INFO GPL-0002] DBU: 2000
[INFO GPL-0003] SiteSize: 380 2800
[INFO GPL-0004] CoreAreaLxLy: 3800 5600
[INFO GPL-0005] CoreAreaUxUy: 57000 56000
[INFO GPL-0006] NumInstances: 60
[INFO GPL-0007] NumPlaceInstances: 24
[INFO GPL-0008] NumFixedInstances: 36
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 35
[INFO GPL-0011] NumPins: 98
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 60800 60800
[INFO GPL-0014] CoreAreaLxLy: 3800 5600
[INFO GPL-0015] CoreAreaUxUy: 57000 56000
[INFO GPL-0016] CoreArea: 2681280000
[INFO GPL-0017] NonPlaceInstsArea: 38304000
[INFO GPL-0018] PlaceInstsArea: 370272000
[INFO GPL-0019] Util(%): 14.01
[INFO GPL-0020] StdInstsArea: 370272000
[INFO GPL-0021] MacroInstsArea: 0
[InitialPlace] Iter: 1 CG Error: 0.00000001 HPWL: 465570
[InitialPlace] Iter: 2 CG Error: 0.00000005 HPWL: 448410
[InitialPlace] Iter: 3 CG Error: 0.00000010 HPWL: 448637
[InitialPlace] Iter: 4 CG Error: 0.00000008 HPWL: 447337
[InitialPlace] Iter: 5 CG Error: 0.00000007 HPWL: 445194
[INFO GPL-0031] FillerInit: NumGCells: 52
[INFO GPL-0032] FillerInit: NumGNets: 35
[INFO GPL-0033] FillerInit: NumGPins: 98
[INFO GPL-0023] TargetDensity: 0.30
[INFO GPL-0024] AveragePlaceInstArea: 15428000
[INFO GPL-0025] IdealBinArea: 51426664
[INFO GPL-0026] IdealBinCnt: 52
[INFO GPL-0027] TotalBinArea: 2681280000
[INFO GPL-0028] BinCnt: 4 4
[INFO GPL-0029] BinSize: 13300 12600
[INFO GPL-0030] NumBins: 16
[NesterovSolve] Iter: 1 overflow: 0.430268 HPWL: 206740
[NesterovSolve] Snapshot saved at iter = 0
[NesterovSolve] Iter: 10 overflow: 0.401159 HPWL: 215670
[NesterovSolve] Iter: 20 overflow: 0.387865 HPWL: 218420
[NesterovSolve] Iter: 30 overflow: 0.425918 HPWL: 220465
[NesterovSolve] Iter: 40 overflow: 0.429341 HPWL: 219979
[NesterovSolve] Iter: 50 overflow: 0.429173 HPWL: 219679
[NesterovSolve] Iter: 60 overflow: 0.427407 HPWL: 219187
[NesterovSolve] Iter: 70 overflow: 0.426848 HPWL: 218947
[NesterovSolve] Iter: 80 overflow: 0.426691 HPWL: 219249
[NesterovSolve] Iter: 90 overflow: 0.428632 HPWL: 219423
[NesterovSolve] Iter: 100 overflow: 0.42885 HPWL: 219384
[NesterovSolve] Iter: 110 overflow: 0.428452 HPWL: 219370
[NesterovSolve] Iter: 120 overflow: 0.427572 HPWL: 219454
[NesterovSolve] Iter: 130 overflow: 0.427621 HPWL: 219748
[NesterovSolve] Iter: 140 overflow: 0.428161 HPWL: 220009
[NesterovSolve] Iter: 150 overflow: 0.42833 HPWL: 220040
[NesterovSolve] Iter: 160 overflow: 0.428066 HPWL: 220205
[NesterovSolve] Iter: 170 overflow: 0.427224 HPWL: 220847
[NesterovSolve] Iter: 180 overflow: 0.426521 HPWL: 220272
[NesterovSolve] Iter: 190 overflow: 0.426841 HPWL: 220601
[NesterovSolve] Iter: 200 overflow: 0.426326 HPWL: 220365
[NesterovSolve] Iter: 210 overflow: 0.4245 HPWL: 220858
[NesterovSolve] Iter: 220 overflow: 0.420063 HPWL: 221996
[NesterovSolve] Iter: 230 overflow: 0.406495 HPWL: 224016
[NesterovSolve] Iter: 240 overflow: 0.382397 HPWL: 223982
[NesterovSolve] Iter: 250 overflow: 0.33548 HPWL: 226575
[NesterovSolve] Iter: 260 overflow: 0.290903 HPWL: 227775
[NesterovSolve] Iter: 270 overflow: 0.234208 HPWL: 230142
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
[INFO GRT-0020] Min routing layer: metal1
[INFO GRT-0021] Max routing layer: metal10
[INFO GRT-0022] Global adjustment: 0%
[INFO GRT-0023] Grid origin: (0, 0)
[WARNING GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0224] Chose via via1_4 as default.
[INFO GRT-0224] Chose via via2_8 as default.
[INFO GRT-0224] Chose via via3_2 as default.
[INFO GRT-0224] Chose via via4_0 as default.
[INFO GRT-0224] Chose via via5_0 as default.
[INFO GRT-0224] Chose via via6_0 as default.
[INFO GRT-0224] Chose via via7_0 as default.
[INFO GRT-0224] Chose via via8_0 as default.
[INFO GRT-0224] Chose via via9_0 as default.
[INFO GRT-0088] Layer metal1 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1350
[INFO GRT-0088] Layer metal2 Track-Pitch = 0.1900 line-2-Via Pitch: 0.1400
[INFO GRT-0088] Layer metal3 Track-Pitch = 0.1400 line-2-Via Pitch: 0.1400
[INFO GRT-0088] Layer metal4 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800
[INFO GRT-0088] Layer metal5 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800
[INFO GRT-0088] Layer metal6 Track-Pitch = 0.2800 line-2-Via Pitch: 0.2800
[INFO GRT-0088] Layer metal7 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000
[INFO GRT-0088] Layer metal8 Track-Pitch = 0.8000 line-2-Via Pitch: 0.8000
[INFO GRT-0088] Layer metal9 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000
[INFO GRT-0088] Layer metal10 Track-Pitch = 1.6000 line-2-Via Pitch: 1.6000
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 298
[INFO GRT-0019] Found 1 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 10
[INFO GRT-0017] Processing 817 blockages on layer metal1.
[INFO GRT-0053] Routing resources analysis:
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
metal1 Horizontal 2940 2731 7.11%
metal2 Vertical 2156 2041 5.33%
metal3 Horizontal 2940 2795 4.93%
metal4 Vertical 1372 1313 4.30%
metal5 Horizontal 1372 1313 4.30%
metal6 Vertical 1372 1313 4.30%
metal7 Horizontal 392 364 7.14%
metal8 Vertical 392 364 7.14%
metal9 Horizontal 196 169 13.78%
metal10 Vertical 196 169 13.78%
---------------------------------------------------------------
[INFO GRT-0111] Final number of vias: 26
[INFO GRT-0112] Final usage 3D: 132
[INFO GRT-0096] Final congestion report:
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
metal1 2731 35 1.28% 0 / 0 / 0
metal2 2041 19 0.93% 0 / 0 / 0
metal3 2795 0 0.00% 0 / 0 / 0
metal4 1313 0 0.00% 0 / 0 / 0
metal5 1313 0 0.00% 0 / 0 / 0
metal6 1313 0 0.00% 0 / 0 / 0
metal7 364 0 0.00% 0 / 0 / 0
metal8 364 0 0.00% 0 / 0 / 0
metal9 169 0 0.00% 0 / 0 / 0
metal10 169 0 0.00% 0 / 0 / 0
---------------------------------------------------------------------------------------
Total 12572 54 0.43% 0 / 0 / 0
[INFO GRT-0018] Total wirelength: 214 um
[INFO GPL-0036] TileLxLy: 0 0
[INFO GPL-0037] TileSize: 4200 4200
[INFO GPL-0038] TileCnt: 14 15
[INFO GPL-0039] numRoutingLayers: 10
[INFO GPL-0040] NumTiles: 210
[INFO GPL-0063] TotalRouteOverflowH2: 0.0
[INFO GPL-0064] TotalRouteOverflowV2: 0.0
[INFO GPL-0065] OverflowTileCnt2: 0
[INFO GPL-0066] 0.5%RC: 0.7600000143051148
[INFO GPL-0067] 1.0%RC: 0.6296296450826857
[INFO GPL-0068] 2.0%RC: 0.3629629732006126
[INFO GPL-0069] 5.0%RC: 0.19069768072560775
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 0.6948148
[NesterovSolve] Iter: 280 overflow: 0.173147 HPWL: 232499
[NesterovSolve] Iter: 290 overflow: 0.129757 HPWL: 236163
[NesterovSolve] Iter: 300 overflow: 0.101423 HPWL: 241453
[NesterovSolve] Finished with Overflow: 0.099384
| INFO | job0 | place | 0 | Writing manifest to /mnt/c/Users/haray/home/siliconcompiler/siliconcompiler/build/heartbeat/job0/place
/0/outputs/heartbeat.pkg.json
[INFO RSZ-0027] Inserted 1 input buffers.
[INFO RSZ-0028] Inserted 1 output buffers.
[INFO RSZ-0058] Using max wire length 853um.
[INFO RSZ-0039] Resized 1 instances.
[WARNING DPL-0011] Could not find power special net.
Placement Analysis
---------------------------------
total displacement 59.5 u
average displacement 1.0 u
max displacement 3.8 u
original HPWL 121.8 u
legalized HPWL 209.7 u
delta HPWL 72 %
[INFO DPL-0020] Mirrored 7 instances
[INFO DPL-0021] HPWL before 209.7 u
[INFO DPL-0022] HPWL after 206.2 u
[INFO DPL-0023] HPWL delta -1.7 %
SC_METRIC: report_checks -path_delay max
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
7.28 0.11 0.11 ^ _72_/Q (DFFR_X1)
8.36 0.08 0.19 ^ _43_/ZN (AND4_X1)
4.46 0.04 0.23 v _46_/ZN (NAND4_X1)
1.17 0.04 0.28 v _54_/ZN (XNOR2_X1)
0.00 0.28 v _79_/D (DFFR_X1)
0.28 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ _79_/CK (DFFR_X1)
-0.04 0.96 library setup time
0.96 data required time
----------------------------------------------------------------
0.96 data required time
-0.28 data arrival time
----------------------------------------------------------------
0.68 slack (MET)
SC_METRIC: report_checks -path_delay min
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
1.28 0.06 0.06 ^ _72_/QN (DFFR_X1)
0.00 0.06 ^ _72_/D (DFFR_X1)
0.06 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _72_/CK (DFFR_X1)
0.01 0.01 library hold time
0.01 data required time
----------------------------------------------------------------
0.01 data required time
-0.06 data arrival time
----------------------------------------------------------------
0.06 slack (MET)
SC_METRIC: unconstrained
Startpoint: _72_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _79_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Delay Time Description
----------------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _72_/CK (DFFR_X1)
7.28 0.11 0.11 ^ _72_/Q (DFFR_X1)
8.36 0.08 0.19 ^ _43_/ZN (AND4_X1)
4.46 0.04 0.23 v _46_/ZN (NAND4_X1)
1.17 0.04 0.28 v _54_/ZN (XNOR2_X1)
0.00 0.28 v _79_/D (DFFR_X1)
0.28 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock network delay (ideal)
0.00 1.00 clock reconvergence pessimism
1.00 ^ _79_/CK (DFFR_X1)
-0.04 0.96 library setup time
0.96 data required time
----------------------------------------------------------------
0.96 data required time
-0.28 data arrival time
----------------------------------------------------------------
0.68 slack (MET)
SC_METRIC: wns
wns 0.00
SC_METRIC: tns
tns 0.00
SC_METRIC: setupslack
worst slack 0.68
SC_METRIC: holdslack
worst slack 0.06
SC_METRIC: power
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 3.86e-05 1.29e-06 5.82e-07 4.05e-05 95.8%
Combinational 7.72e-07 5.37e-07 4.71e-07 1.78e-06 4.2%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.94e-05 1.83e-06 1.05e-06 4.23e-05 100.0%
93.2% 4.3% 2.5%
SC_METRIC: cellarea
Design area 69 u^2 10% utilization.
````
Design area は全体の10%のままでした。
# クロックツリー (cts)
ここからは、クロックツリー (cts) です。
| INFO | job0 | cts | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/cts/0/sc_manifest.tcl | INFO | job0 | cts | 0 | Running in /XXXXX/build/heratbeat/job0/cts/0 | INFO | job0 | cts | 0 | openroad -no_init -exit /XXXXX/siliconcompiler/tools/openroad/sc_apr.tcl | INFO | job0 | cts | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/cts/0/outputs/heartbeat.pkg.json OpenROAD 1 v2.0-880-gd1c7001ad This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef [INFO ODB-0223] Created 22 technology layers [INFO ODB-0224] Created 27 technology vias [INFO ODB-0226] Finished LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/pdk/r1p0/apr/freepdk45.tech.lef [INFO ODB-0222] Reading LEF file: /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: /XXXXX/iliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lef/NangateOpenCellLibrary.macro.mod.lef [INFO ODB-0127] Reading DEF file: inputs/heartbeat.def [INFO ODB-0128] Design: heartbeat [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 62 components and 223 component-terminals. [INFO ODB-0133] Created 37 nets and 99 connections. [INFO ODB-0134] Finished DEF file: inputs/heartbeat.def [INFO CTS-0039] Number of created patterns = 11880. [INFO CTS-0084] Compiling LUT. Min. len Max. len Min. cap Max. cap Min. slew Max. slew 2 8 1 34 1 15 [WARNING CTS-0043] 1584 wires are pure wire and no slew degradation. TritonCTS forced slew degradation on these wires. [INFO CTS-0046] Number of wire segments: 11880. [INFO CTS-0047] Number of keys in characterization LUT: 1602. [INFO CTS-0048] Actual min input cap: 1. [INFO CTS-0007] Net "clk" found for clock "clk". [INFO CTS-0010] Clock net "clk" has 9 sinks. [INFO CTS-0008] TritonCTS found 1 clock nets. [INFO CTS-0097] Characterization used 1 buffer(s) types. [INFO CTS-0027] Generating H-Tree topology for net clk. [INFO CTS-0028] Total number of sinks: 9. [INFO CTS-0029] Sinks will be clustered in groups of up to 30 and with maximum cluster diameter of 100.0 um. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 14000 dbu (7 um). [INFO CTS-0021] Distance between buffers: 7 units (100 um). [INFO CTS-0023] Original sink region: [(11135, 27020), (43435, 32620)]. [INFO CTS-0024] Normalized sink region: [(0.795357, 1.93), (3.1025, 2.33)]. [INFO CTS-0025] Width: 2.3071. [INFO CTS-0026] Height: 0.4000. [WARNING CTS-0045] Creating fake entries in the LUT. Level 1 Direction: Horizontal Sinks per sub-region: 5 Sub-region size: 1.1536 X 0.4000 [INFO CTS-0034] Segment length (rounded): 1. Key: 11914 outSlew: 2 load: 1 length: 1 isBuffered: false [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 9. [INFO CTS-0036] Average source sink dist: 13328.33 dbu. [INFO CTS-0037] Number of outlier sinks: 0. [INFO CTS-0018] Created 3 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [INFO CTS-0015] Created 3 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 4:1, 5:1.. [INFO CTS-0017] Max level of the clock tree: 1. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 9 [INFO CTS-0100] Leaf buffers 0 [INFO CTS-0101] Average sink wire length 41.8 um [INFO CTS-0102] Path depth 2 - 2 [INFO RSZ-0058] Using max wire length 853um. [WARNING DPL-0011] Could not find power special net.
Placement Analysis
total displacement 12.2 u average displacement 0.2 u max displacement 2.8 u original HPWL 234.2 u legalized HPWL 243.4 u delta HPWL 4 %
[INFO RSZ-0033] No hold violations found. [WARNING DPL-0011] Could not find power special net.
Placement Analysis
total displacement 0.0 u average displacement 0.0 u max displacement 0.0 u original HPWL 243.4 u legalized HPWL 243.4 u delta HPWL 0 %
SC_METRIC: report_checks -path_delay max Startpoint: 72 (rising edge-triggered flip-flop clocked by clk) Endpoint: 79 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max
Cap Delay Time Description
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.60 0.00 0.00 ^ clk (in) 6.91 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 3.99 0.02 0.04 ^ clkbuf_1_0f_clk/Z (BUF_X4) 0.00 0.04 ^ 72/CK (DFFR_X1) 7.30 0.11 0.15 ^ 72/Q (DFFR_X1) 8.38 0.08 0.23 ^ 43/ZN (AND4_X1) 4.47 0.04 0.27 v 46/ZN (NAND4_X1) 1.21 0.04 0.32 v 54/ZN (XNOR2_X1) 0.00 0.32 v 79/D (DFFR_X1) 0.32 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock source latency
3.60 0.00 1.00 ^ clk (in) 6.91 0.02 1.02 ^ clkbuf_0_clk/Z (BUF_X4) 4.98 0.02 1.04 ^ clkbuf_1_1f_clk/Z (BUF_X4) 0.00 1.04 ^ 79/CK (DFFR_X1) 0.00 1.04 clock reconvergence pessimism -0.04 1.00 library setup time
1.00 data required time
1.00 data required time
-0.32 data arrival time
0.68 slack (MET)
SC_METRIC: report_checks -path_delay min Startpoint: 72 (rising edge-triggered flip-flop clocked by clk) Endpoint: 72 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min
Cap Delay Time Description
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.60 0.00 0.00 ^ clk (in) 6.91 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 3.99 0.02 0.04 ^ clkbuf_1_0f_clk/Z (BUF_X4) 0.00 0.04 ^ 72/CK (DFFR_X1) 1.28 0.07 0.10 ^ 72/QN (DFFR_X1) 0.00 0.10 ^ 72/D (DFFR_X1) 0.10 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.60 0.00 0.00 ^ clk (in) 6.91 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 3.99 0.02 0.04 ^ clkbuf_1_0f_clk/Z (BUF_X4) 0.00 0.04 ^ 72/CK (DFFR_X1) 0.00 0.04 clock reconvergence pessimism 0.01 0.04 library hold time
0.04 data required time
0.04 data required time
-0.10 data arrival time
0.06 slack (MET)
SC_METRIC: unconstrained Startpoint: 72 (rising edge-triggered flip-flop clocked by clk) Endpoint: 79 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max
Cap Delay Time Description
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
3.60 0.00 0.00 ^ clk (in) 6.91 0.02 0.02 ^ clkbuf_0_clk/Z (BUF_X4) 3.99 0.02 0.04 ^ clkbuf_1_0f_clk/Z (BUF_X4) 0.00 0.04 ^ 72/CK (DFFR_X1) 7.30 0.11 0.15 ^ 72/Q (DFFR_X1) 8.38 0.08 0.23 ^ 43/ZN (AND4_X1) 4.47 0.04 0.27 v 46/ZN (NAND4_X1) 1.21 0.04 0.32 v 54/ZN (XNOR2_X1) 0.00 0.32 v 79/D (DFFR_X1) 0.32 data arrival time
1.00 1.00 clock clk (rise edge)
0.00 1.00 clock source latency
3.60 0.00 1.00 ^ clk (in) 6.91 0.02 1.02 ^ clkbuf_0_clk/Z (BUF_X4) 4.98 0.02 1.04 ^ clkbuf_1_1f_clk/Z (BUF_X4) 0.00 1.04 ^ 79/CK (DFFR_X1) 0.00 1.04 clock reconvergence pessimism -0.04 1.00 library setup time
1.00 data required time
1.00 data required time
-0.32 data arrival time
0.68 slack (MET)
SC_METRIC: wns wns 0.00 SC_METRIC: tns tns 0.00 SC_METRIC: setupslack worst slack 0.68 SC_METRIC: holdslack worst slack 0.06 SC_METRIC: power Group Internal Switching Leakage Total
Power Power Power Power
Sequential 3.84e-05 1.30e-06 5.82e-07 4.03e-05 36.1% Combinational 5.07e-05 1.98e-05 7.29e-07 7.12e-05 63.9% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Total 8.91e-05 2.11e-05 1.31e-06 1.11e-04 100.0% 79.9% 18.9% 1.2% SC_METRIC: cellarea Design area 74 u2 11% utilization.
Design area は全体の11 %のようです。place後から1%増えました。 # おわりに 今回はクロックツリー(cts) までです。次回は 配置 (route) 以降を見てみます。
