# はじめに
SiliconCompilerの下記のサンプルコード (heartbeat.v)を使ったログを眺めてみます。
hearbeat.v
module heartbeat #(parameter N = 8) ( //inputs input clk,// clock input nreset,//async active low reset output reg out //heartbeat ); reg [N-1:0] counter_reg; always @ (posedge clk or negedge nreset) if(!nreset) begin counter_reg <= 'b0; out <= 1'b0; end else begin counter_reg[N-1:0] <= counter_reg[N-1:0] + 1'b1; out <= (counter_reg[N-1:0]=={(N){1'b1}}); end endmodule
制約ファイル(heartbeat.sdc)
cat heartbeat.sdc
create_clock -name clk -period 1 [get_ports {clk}]
heartbeat.py
import siliconcompiler # import python package chip = siliconcompiler.Chip() # create chip object chip.set('source', 'heartbeat.v') # define list of source files chip.set('design', 'heartbeat') # set top module chip.set('constraint', 'heartbeat.sdc') # set constraints file chip.target('freepdk45') # load predefined target #chip.set('remote', False) # start of flowgraph setup chip.run() # run compilation chip.summary() # print results summary chip.show() # show layout file
SiliconCompiler を実行
今回は、論理合成までです。
環境設定をして、下記のコマンドを実行。最初は、デザインの heartbeat.v の読み込みの部分。読み込みは、surelog にて行われています。
build というディレクトリを作って、その下で作業をするようです。
python hearbeat.py
| INFO | job0 | --- | - | Loading target 'asicflow_freepdk45' | INFO | job0 | --- | - | Loading function 'setup_flow' from module 'asicflow' | INFO | job0 | --- | - | Loading function 'setup_pdk' from module 'freepdk45' | INFO | job0 | --- | - | Operating in 'asic' mode | INFO | job0 | import | 0 | Waiting for inputs... | INFO | job0 | floorplan | 0 | Waiting for inputs... | INFO | job0 | syn | 0 | Waiting for inputs... | INFO | job0 | physyn | 0 | Waiting for inputs... | INFO | job0 | place | 0 | Waiting for inputs... | INFO | job0 | cts | 0 | Waiting for inputs... | INFO | job0 | route | 0 | Waiting for inputs... | INFO | job0 | dfm | 0 | Waiting for inputs... | INFO | job0 | export | 0 | Waiting for inputs... | INFO | job0 | import | 0 | Collecting input sources | INFO | job0 | import | 0 | Copying /XXXXX/heartbeat.v to 'inputs' directory | INFO | job0 | import | 0 | Copying /XXXXX/heartbeat.sdc to 'inputs' directory | INFO | job0 | import | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/import/0/sc_manifest.tcl | INFO | job0 | import | 0 | Running in /XXXXX/build/heartbeat/job0/import/0 | INFO | job0 | import | 0 | surelog -parse /XXXXX/heartbeat.v -top heartbeat +libext+.sv | INFO | job0 | import | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/import/0/outputs/heratbeat.pkg.json [INF:CM0023] Creating log file ./slpp_all/surelog.log. [WRN:PA0205] /XXXXX/heartbeat.v:1: No timescale set for "heartbeat". [INF:CP0300] Compilation... [INF:CP0303] /XXXXX/heartbeat.v:1: Compile module "work@heartbeat". [INF:CP0302] /usr/local/bin/../lib/surelog/sv/builtin.sv:4: Compile class "work@mailbox". [INF:CP0302] /usr/local/bin/../lib/surelog/sv/builtin.sv:33: Compile class "work@process". [INF:CP0302] /usr/local/bin/../lib/surelog/sv/builtin.sv:58: Compile class "work@semaphore". [INF:EL0526] Design Elaboration... [NTE:EL0503] /XXXXX/heartbeat.v:1: Top level module "work@heartbeat". [NTE:EL0508] Nb Top level modules: 1. [NTE:EL0509] Max instance depth: 1. [NTE:EL0510] Nb instances: 1. [NTE:EL0511] Nb leaf instances: 1. [INF:UH0706] Creating UHDM Model... [INF:UH0708] Writing UHDM DB: ./slpp_all//surelog.uhdm... [ FATAL] : 0 [ SYNTAX] : 0 [ ERROR] : 0 [WARNING] : 1 [ NOTE] : 5
上記のように、FATAL/SYNTAX/ERROR等のエラーが無いと、次のステップに進みます。
論理合成 (syn)
ここからは論理合成 (syn)です。実態は、yosys を実行しています。何かの処理をすると、最適化を行うとういう繰り返しです。
| INFO | job0 | syn | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/syn/0/sc_manifest .tcl | INFO | job0 | syn | 0 | Running in /XXXXX/build/heartbeat/job0/syn/0 | INFO | job0 | syn | 0 | yosys -c /XXXXX/siliconcompiler/tools/yosys/sc_syn.tcl /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3672 (git sha1 014c7e26b, gcc 9.3.0-17ubuntu1~20.04 -fPIC -Os) echo on yosys> read_verilog -sv inputs/heartbeat.v 1. Executing Verilog-2005 frontend: inputs/heartbeat.v Parsing SystemVerilog input from `inputs/heartbeat.v' to AST representation. Generating RTLIL representation for module `\heartbeat'. Successfully finished Verilog frontend.
Verilog HDLコード (inputs/heartbeat.v)を読み込んでいます。
yosys> chparam -list heartbeat: yosys> read_liberty -lib /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib 2. Executing Liberty frontend. Imported 134 cell types from liberty file.
freepdk45のLiberty fileをロードしています。
yosys> hierarchy -top heartbeat 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \heartbeat 3.2. Analyzing design hierarchy.. Top module: \heartbeat Removed 0 unused modules.
TOP階層として、heartbeat を指定しています。
yosys> synth -flatten -top heartbeat 4. Executing SYNTH pass.
フラットにして論理合成をしています。
yosys> hierarchy -check -top heartbeat 4.1. Executing HIERARCHY pass (managing design hierarchy). 4.1.1. Analyzing design hierarchy.. Top module: \heartbeat 4.1.2. Analyzing design hierarchy.. Top module: \heartbeat Removed 0 unused modules.
論理合成後の階層をチェックしています。
yosys> proc 4.2. Executing PROC pass (convert processes to netlists). yosys> proc_clean 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. yosys> proc_rmdead 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. yosys> proc_prune 4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 0 assignments to connections.
ここで、2か所、冗長な assignment が削除されていますね。
yosys> proc_init
4.2.4. Executing PROC_INIT pass (extract init attributes).
yosys> proc_arst
4.2.5. Executing PROC_ARST pass (detect async resets in processes).
yosys> proc_mux
4.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\heartbeat.$proc$inputs/heartbeat.v:11$1'.
1/2: $0\out[0:0]
2/2: $0\counter_reg[7:0]
out と counter_reg は、mux を使っていますので、ここで処理されていますね。
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
counter_reg <= 'b0;
out <= 1'b0;
end
else
begin
counter_reg[N-1:0] <= counter_reg[N-1:0] + 1'b1;
out <= (counter_reg[N-1:0]=={(N){1'b1}});
end
yosys> proc_dlatch 4.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). yosys> proc_dff 4.2.8. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\heartbeat.\out' using process `\heartbeat.$proc$inputs/heartbeat.v:11$1'. created $adff cell `$procdff$5' with positive edge clock and negative level reset. Creating register for signal `\heartbeat.\counter_reg' using process `\heartbeat.$proc$inputs/heartbeat.v:11$1'. created $adff cell `$procdff$6' with positive edge clock and negative level reset.
ここでは、Flipflop の処理をしていますね。
yosys> proc_clean 4.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `heartbeat.$proc$inputs/heartbeat.v:11$1'. Cleaned up 0 empty switches.
ネットリストへの変換を行っています。
yosys> flatten 4.3. Executing FLATTEN pass (flatten design).
フラットにしています。
yosys> opt_expr 4.4. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat.
最適化 : 固定値の削除
yosys> opt_clean 4.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. Removed 1 unused cells and 3 unused wires. <suppressed ~2 debug messages>
最適化 : 使っていないセルや配線の削除。１つのセルと、３つの配線が削除されていますね。
yosys> check 4.6. Executing CHECK pass (checking for obvious problems). checking module heartbeat.. found and reported 0 problems.
チェック
yosys> opt -nodffe -nosdff 4.7. Executing OPT pass (performing simple optimizations). yosys> opt_expr 4.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge -nomux 4.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_muxtree 4.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \heartbeat.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. yosys> opt_reduce 4.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 4.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff -nodffe -nosdff 4.7.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> opt_expr 4.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 4.7.9. Finished OPT passes. (There is nothing left to do.)
最適化 : いろいろ
yosys> fsm 4.8. Executing FSM pass (extract and optimize FSM). yosys> fsm_detect 4.8.1. Executing FSM_DETECT pass (finding FSMs in design). yosys> fsm_extract 4.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). yosys> fsm_opt 4.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). yosys> opt_clean 4.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> fsm_opt 4.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). yosys> fsm_recode 4.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). yosys> fsm_info 4.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). yosys> fsm_map 4.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
FSMの処理
yosys> opt 4.9. Executing OPT pass (performing simple optimizations). yosys> opt_expr 4.9.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge -nomux 4.9.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_muxtree 4.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \heartbeat.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. yosys> opt_reduce 4.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 4.9.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 4.9.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> opt_expr 4.9.8. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 4.9.9. Finished OPT passes. (There is nothing left to do.) yosys> wreduce 4.10. Executing WREDUCE pass (reducing word size of cells). yosys> peepopt 4.11. Executing PEEPOPT pass (run peephole optimizers). yosys> opt_clean 4.12. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat..
最適化 : いろいろ
yosys> alumacc 4.13. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module heartbeat: creating $macc model for $add$inputs/heartbeat.v:19$3 ($add). creating $alu model for $macc $add$inputs/heartbeat.v:19$3. creating $alu cell for $add$inputs/heartbeat.v:19$3: $auto$alumacc.cc:485:replace_alu$7 created 1 $alu and 0 $macc cells.
ALU/MACCの置き換え、ALU の置き換えが発生しましたね。下記のcount_regのインクリメントの部分でしょうかね。
always @ (posedge clk or negedge nreset)
if(!nreset)
begin
counter_reg <= 'b0;
out <= 1'b0;
end
else
begin
counter_reg[N-1:0] <= counter_reg[N-1:0] + 1'b1;
out <= (counter_reg[N-1:0]=={(N){1'b1}});
end
yosys> share 4.14. Executing SHARE pass (SAT-based resource sharing).
リソースシェアリング
yosys> opt 4.15. Executing OPT pass (performing simple optimizations). yosys> opt_expr 4.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge -nomux 4.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_muxtree 4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \heartbeat.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. yosys> opt_reduce 4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 4.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 4.15.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> opt_expr 4.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 4.15.9. Finished OPT passes. (There is nothing left to do.)
最適化 : いろいろ
yosys> memory -nomap 4.16. Executing MEMORY pass.
メモリ関連
yosys> opt_mem 4.16.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. yosys> memory_dff 4.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). yosys> opt_clean 4.16.3. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> memory_share 4.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). yosys> opt_clean 4.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> memory_collect 4.16.6. Executing MEMORY_COLLECT pass (generating $mem cells). yosys> opt_clean 4.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat..
最適化 : メモリ関連いろいろ
yosys> opt -fast -full 4.18. Executing OPT pass (performing simple optimizations). yosys> opt_expr -full 4.18.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge 4.18.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 4.18.3. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. 4.18.5. Finished fast OPT passes.
最適化 : fast OPTの終了
yosys> memory_map 4.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
メモリを論理とフリップフロップに変換
yosys> opt -full 4.20. Executing OPT pass (performing simple optimizations). yosys> opt_expr -full 4.20.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge -nomux 4.20.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_muxtree 4.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \heartbeat.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. yosys> opt_reduce -full 4.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 4.20.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_share 4.20.6. Executing OPT_SHARE pass. yosys> opt_dff 4.20.7. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> opt_expr -full 4.20.9. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 4.20.10. Finished OPT passes. (There is nothing left to do.)
最適化 : 全体
yosys> techmap 4.21. Executing TECHMAP pass (map to technology primitives). 4.21.1. Executing Verilog-2005 frontend: /XXXXX/siliconcompiler/third_party/tools/openroad/tools/install/yosys/bin/../share/yosys/techmap.v Parsing Verilog input from `/XXXXX/siliconcompiler/third_party/tools/openroad/tools/install/yosys/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 4.21.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $eq. Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=8\Y_WIDTH=8 for cells of type $alu. Using extmapper simplemap for cells of type $adff. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $and. Using template $paramod\_90_lcu\WIDTH=8 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. No more expansions possible. <suppressed ~271 debug messages>
yosys> opt -fast 4.22. Executing OPT pass (performing simple optimizations). yosys> opt_expr osys> opt_expr 4.22.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. <suppressed ~51 debug messages> yosys> opt_merge 4.22.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. <suppressed ~27 debug messages> Removed a total of 9 cells.
９個のセルが削除されていますね。
yosys> opt_dff 4.22.3. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. Removed 3 unused cells and 47 unused wires. <suppressed ~4 debug messages>
３個のセルと、４７本の配線が削除されていますね。
4.22.5. Finished fast OPT passes.
yosys> abc -fast 4.23. Executing ABC pass (technology mapping using ABC). 4.23.1. Extracting gate netlist of module `\heartbeat' to `<abc-temp-dir>/input.blif'.. Extracted 31 gates and 39 wires to a netlist network with 8 inputs and 9 outputs. 4.23.1.1. Executing ABC. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_blif <abc-temp-dir>/input.blif ABC: + read_library <abc-temp-dir>/stdcells.genlib ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib". ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif <abc-temp-dir>/output.blif 4.23.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 3 ABC RESULTS: ANDNOT cells: 3 ABC RESULTS: NAND cells: 3 ABC RESULTS: NOT cells: 1 ABC RESULTS: OR cells: 1 ABC RESULTS: ORNOT cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 6 ABC RESULTS: internal signals: 22 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 9 Removing temp directory.
yosys> opt -fast 4.24. Executing OPT pass (performing simple optimizations). yosys> opt_expr 4.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge 4.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 4.24.3. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 4.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. Removed 0 unused cells and 30 unused wires. <suppressed ~1 debug messages>
30本の配線が削除されていますね。
4.24.5. Finished fast OPT passes.
yosys> hierarchy -check 4.25. Executing HIERARCHY pass (managing design hierarchy). 4.25.1. Analyzing design hierarchy.. Top module: \heartbeat 4.25.2. Analyzing design hierarchy.. Top module: \heartbeat Removed 0 unused modules.
チェック
yosys> stat
4.26. Printing statistics.
=== heartbeat ===
Number of wires: 17
Number of wire bits: 38
Number of public wires: 4
Number of public wire bits: 11
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 28
$_ANDNOT_ 3
$_AND_ 3
$_DFF_PN0_ 9
$_NAND_ 3
$_NOT_ 1
$_ORNOT_ 1
$_OR_ 1
$_XNOR_ 1
$_XOR_ 6
統計データの出力
yosys> check 4.27. Executing CHECK pass (checking for obvious problems). checking module heartbeat.. found and reported 0 problems. yosys> opt -purge 5. Executing OPT pass (performing simple optimizations). yosys> opt_expr 5.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge -nomux 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_muxtree 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \heartbeat.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. yosys> opt_reduce 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 5.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean -purge 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> opt_expr 5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 5.9. Finished OPT passes. (There is nothing left to do.)
もう一度最適化
yosys> techmap -map cells_latch_freepdk45.v
6. Executing TECHMAP pass (map to technology primitives).
6.1. Executing Verilog-2005 frontend: cells_latch_freepdk45.v
Parsing Verilog input from `cells_latch_freepdk45.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.
6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
yosys> dfflibmap -liberty /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib
7. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
cell DFF_X1 (noninv, pins=4, area=4.52) is a direct match for cell type $_DFF_P_.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
cell DFFR_X1 (noninv, pins=5, area=5.32) is a direct match for cell type $_DFF_PN0_.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFRS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFR_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFFS_X2' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X1' - skipping.
Warning: Found unsupported expression 'SE*SI+D*!SE' in pin attribute of cell 'SDFF_X2' - skipping.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\DFF_X1 _DFF_P_ (.CK( C), .D( D), .Q( Q), .QN(~Q));
unmapped dff cell: $_DFF_NN0_
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\DFFR_X1 _DFF_PN0_ (.CK( C), .D( D), .Q( Q), .QN(~Q), .RN( R));
\DFFS_X1 _DFF_PN1_ (.CK( C), .D( D), .Q( Q), .QN(~Q), .SN( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
unmapped dff cell: $_DFFSR_NNN_
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
\DFFRS_X1 _DFFSR_PNN_ (.CK( C), .D( D), .Q( Q), .QN(~Q), .RN( R), .SN( S));
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
yosys> dfflegalize -cell $_DFF_P_ 01 -cell $_DFF_PN0_ 01 -cell $_DFF_PN1_ 01 -cell $_DFFSR_PNN_ 01 t:$_DFF* t:$_SDFF*
7.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\heartbeat':
mapped 9 $_DFF_PN0_ cells to \DFFR_X1 cells.
9個の $_DFF_PN0_cells を \DFFR_X1 にマッピングしていますね。
cells_latch_freepdk45.v へのマッピング
yosys> opt 8. Executing OPT pass (performing simple optimizations). yosys> opt_expr 8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. yosys> opt_merge -nomux 8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_muxtree 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 8.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. Removed 1 unused cells and 2 unused wires. <suppressed ~2 debug messages>
1個のセルと、2本の配線を削除していますね。
yosys> opt_expr 8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 8.9. Finished OPT passes. (There is nothing left to do.) yosys> opt_muxtree 8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \heartbeat.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. yosys> opt_reduce 8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \heartbeat. Performed a total of 0 changes. yosys> opt_merge 8.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\heartbeat'. Removed a total of 0 cells. yosys> opt_dff 8.13. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean 8.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \heartbeat.. yosys> opt_expr 8.15. Executing OPT_EXPR pass (perform const folding). Optimizing module heartbeat. 8.16. Finished OPT passes. (There is nothing left to do.)
最適化
yosys> abc -liberty /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib 9. Executing ABC pass (technology mapping using ABC). 9.1. Extracting gate netlist of module `\heartbeat' to `<abc-temp-dir>/input.blif'.. Extracted 18 gates and 26 wires to a netlist network with 8 inputs and 8 outputs. 9.1.1. Executing ABC. Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_blif <abc-temp-dir>/input.blif ABC: + read_lib -w /mnt/c/Users/haray/home/siliconcompiler/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/li b/NangateOpenCellLibrary_typical.lib ABC: Parsing finished successfully. Parsing time = 0.08 sec ABC: Scl_LibertyReadGenlib() skipped cell "ANTENNA_X1" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATETST_X1" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATETST_X2" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATETST_X4" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATETST_X8" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATE_X1" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATE_X2" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATE_X4" without logic function. ABC: Scl_LibertyReadGenlib() skipped cell "CLKGATE_X8" without logic function. ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFRS_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFRS_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFR_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFR_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFS_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFS_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DLH_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DLH_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DLL_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "DLL_X2". ABC: Scl_LibertyReadGenlib() skipped cell "FILLCELL_X1" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "FILLCELL_X2" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "FILLCELL_X4" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "FILLCELL_X8" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "FILLCELL_X16" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "FILLCELL_X32" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "LOGIC0_X1" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped cell "LOGIC1_X1" due to dont_use attribute. ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFFRS_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFFRS_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFFR_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFFR_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFFS_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFFS_X2". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFF_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "SDFF_X2". ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUF_X1". ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUF_X2". ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUF_X4". ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUF_X8". ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUF_X16". ABC: Scl_LibertyReadGenlib() skipped three-state cell "TINV_X1". ABC: Scl_LibertyReadGenlib() skipped sequential cell "TLAT_X1". ABC: Library "NangateOpenCellLibrary" from "/mnt/c/Users/haray/home/siliconcompiler/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/Nanga teOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib" has 90 cells (35 skipped: 21 seq; 6 tri-state; 8 no func; 9 dont_use). Time = 0.09 sec ABC: Memory = 8.88 MB. Time = 0.09 sec ABC: Warning: Detected 2 multi-output gates (for example, "FA_X1"). ABC: + strash ABC: + ifraig ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf ABC: + &put ABC: + write_blif <abc-temp-dir>/output.blif 9.1.2. Re-integrating ABC results. ABC RESULTS: AND4_X1 cells: 1 ABC RESULTS: INV_X1 cells: 1 ABC RESULTS: NAND2_X1 cells: 2 ABC RESULTS: NAND3_X1 cells: 2 ABC RESULTS: NAND4_X1 cells: 1 ABC RESULTS: NOR2_X1 cells: 1 ABC RESULTS: XNOR2_X1 cells: 5 ABC RESULTS: XOR2_X1 cells: 2 ABC RESULTS: internal signals: 10 ABC RESULTS: input signals: 8 ABC RESULTS: output signals: 8 Removing temp directory.
ABCで最適化
yosys> stat -liberty /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib
yosys> stat -liberty /XXXXX/siliconcompiler/third_party/pdks/virtual/freepdk45/libs/NangateOpenCellLibrary/r1p0/lib/NangateOpenCellLibrary_typical.lib
10. Printing statistics.
| INFO | job0 | syn | 0 | Writing manifest to /XXXXX/build/heartbeat/job0/syn/0/outputs/heartbeat.pkg.json
=== heartbeat ===
Number of wires: 48
Number of wire bits: 69
Number of public wires: 4
Number of public wire bits: 11
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 24
AND4_X1 1
DFFR_X1 9
INV_X1 1
NAND2_X1 2
NAND3_X1 2
NAND4_X1 1
NOR2_X1 1
XNOR2_X1 5
XOR2_X1 2
Chip area for module '\heartbeat': 67.032000
統計データの出力
yosys> setundef -zero 11. Executing SETUNDEF pass (replace undef values with defined constants). yosys> hilomap -hicell LOGIC1_X1 Z -locell LOGIC0_X1 Z 12. Executing HILOMAP pass (mapping to constant drivers).
固定値の処理
yosys> insbuf -buf BUF_X1 A Z
- Executing INSBUF pass (insert buffer cells for connected wires). Added heartbeat.$auto$insbuf.cc:79:execute$305: \counter_reg [1] -> $auto$alumacc.cc:485:replace_alu$7.X [1] Added heartbeat.$auto$insbuf.cc:79:execute$306: \counter_reg [2] -> $auto$alumacc.cc:485:replace_alu$7.X [2] Added heartbeat.$auto$insbuf.cc:79:execute$307: \counter_reg [3] -> $auto$alumacc.cc:485:replace_alu$7.X [3] Added heartbeat.$auto$insbuf.cc:79:execute$308: \counter_reg [4] -> $auto$alumacc.cc:485:replace_alu$7.X [4] Added heartbeat.$auto$insbuf.cc:79:execute$309: \counter_reg [5] -> $auto$alumacc.cc:485:replace_alu$7.X [5] Added heartbeat.$auto$insbuf.cc:79:execute$310: \counter_reg [6] -> $auto$alumacc.cc:485:replace_alu$7.X [6] Added heartbeat.$auto$insbuf.cc:79:execute$311: \counter_reg [7] -> $auto$alumacc.cc:485:replace_alu$7.X [7] Added heartbeat.$auto$insbuf.cc:79:execute$312: $auto$alumacc.cc:485:replace_alu$7.X [0] -> $auto$alumacc.cc:485:replace_alu$7.Y [0] Added heartbeat.$auto$insbuf.cc:79:execute$313: \counter_reg [1] -> $abc$289$counter_reg[1] Added heartbeat.$auto$insbuf.cc:79:execute$314: \counter_reg [0] -> $abc$289$counter_reg[0] Added heartbeat.$auto$insbuf.cc:79:execute$315: \counter_reg [3] -> $abc$289$counter_reg[3] Added heartbeat.$auto$insbuf.cc:79:execute$316: \counter_reg [2] -> $abc$289$counter_reg[2] Added heartbeat.$auto$insbuf.cc:79:execute$317: \counter_reg [5] -> $abc$289$counter_reg[5] Added heartbeat.$auto$insbuf.cc:79:execute$318: \counter_reg [4] -> $abc$289$counter_reg[4] Added heartbeat.$auto$insbuf.cc:79:execute$319: \counter_reg [6] -> $abc$289$counter_reg[6] Added heartbeat.$auto$insbuf.cc:79:execute$320: \counter_reg [7] -> $abc$289$counter_reg[7] Added heartbeat.$auto$insbuf.cc:79:execute$321: $abc$289$0\out[0:0] -> $0\out[0:0] Added heartbeat.$auto$insbuf.cc:79:execute$322: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[1] -> $auto$alumacc.cc:485:replace_alu$7.Y [1] Added heartbeat.$auto$insbuf.cc:79:execute$323: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[2] -> $auto$alumacc.cc:485:replace_alu$7.Y [2] Added heartbeat.$auto$insbuf.cc:79:execute$324: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[3] -> $auto$alumacc.cc:485:replace_alu$7.Y [3] Added heartbeat.$auto$insbuf.cc:79:execute$325: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[4] -> $auto$alumacc.cc:485:replace_alu$7.Y [4] Added heartbeat.$auto$insbuf.cc:79:execute$326: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[5] -> $auto$alumacc.cc:485:replace_alu$7.Y [5] Added heartbeat.$auto$insbuf.cc:79:execute$327: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[6] -> $auto$alumacc.cc:485:replace_alu$7.Y [6] Added heartbeat.$auto$insbuf.cc:79:execute$328: $abc$289$auto$alumacc.cc:485:replace_alu$7.Y[7] -> $auto$alumacc.cc:485:replace_alu$7.Y [7] ‘‘‘
バッファーセルの追加
yosys> splitnets 14. Executing SPLITNETS pass (splitting up multi-bit signals).
マルチビット信号の分割
yosys> clean Removed 8 unused cells and 18 unused wires. yosys> write_verilog -noattr -noexpr -nohex -nodec outputs/heartbeat.vg 15. Executing Verilog backend. Dumping module `\heartbeat'. Warnings: 8 unique messages, 72 total End of script. Logfile hash: bc0bc04dd1, CPU: user 0.31s system 0.04s, MEM: 53.67 MB peak Yosys 0.9+3672 (git sha1 014c7e26b, gcc 9.3.0-17ubuntu1~20.04 -fPIC -Os) Time spent: 43% 2x abc (0 sec), 14% 1x dfflibmap (0 sec), ...
Verilog HDLのネットリストの生成
おわりに
今日は、論理合成までを見ました。実態は、yosys を実行しています。何かの処理をすると、最適化を行うとういう繰り返しです。
次回は、フロアプラン (floorplan) になります。
