Verification Engineerの戯言
ここで紹介した「SystemVerilog/Verilog HDL関連」のサイトのリンク集です。
SystemVerilog User Group(2007.03.21, http://www.svug.org/)
http://blogs.yahoo.co.jp/verification_engineer/1421632.html
http://blogs.yahoo.co.jp/verification_engineer/3989883.html
Open Verification Library(2007.04.28, http://www.accellera.org/activities/ovl/)
http://blogs.yahoo.co.jp/verification_engineer/4542337.html
http://blogs.yahoo.co.jp/verification_engineer/8549972.html
SCE-MI(2007.05.12, http://www.accellera.org/activities/itc)
http://blogs.yahoo.co.jp/verification_engineer/2617032.html
http://blogs.yahoo.co.jp/verification_engineer/5928360.html
Cadence Designer Network User Group Community(2007.07.12, http://www.cdnusers.org/)
http://blogs.yahoo.co.jp/verification_engineer/12631051.html
GPL Cver(2007.06.02, http://www.pragmatic-c.com/gpl-cver/)
http://blogs.yahoo.co.jp/verification_engineer/8129548.html
Ruby-VPI : Ruby interface to Verilog VPI(2007.08.18, http://ruby-vpi.rubyforge.org/doc/readme.html)
http://blogs.yahoo.co.jp/verification_engineer/17598433.html
Sutherland-hdl(2007.04.23, http://www.sutherland-hdl.com/)
http://blogs.yahoo.co.jp/verification_engineer/4199883.html
Paradigm Works(2007.07.24, http://www.paradigm-works.com)
http://blogs.yahoo.co.jp/verification_engineer/14273757.html
Sunburst Design Inc.(2007.07.26, http://www.sunburst-design.com/)
http://blogs.yahoo.co.jp/verification_engineer/14524502.html
einfochips(2007.07.30, http://www.einfochips.com/)
http://blogs.yahoo.co.jp/verification_engineer/14966520.html
Xilinx : ModelSim XE(2007.08.16, http://www.xilinx.co.jp)
http://blogs.yahoo.co.jp/verification_engineer/17376018.html
システムデザインフォーラム2007(2007.07.21, http://eda.ics.es.osaka-u.ac.jp/jeita/eda/english/users_lib/systemdesignforum2007.html
http://blogs.yahoo.co.jp/verification_engineer/13800946.html
