UVM 1.0 : UVM Run-Time Phases Primer (その2)

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SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

uvm_componentクラスは、次の3つのvirtual関数があります。

    phase_started
    phase_ready_to_end
    phase_ended

これら3つのvirtual関数には、uvm_component.svファイルで次のようなコメントがあります。

  // Function: phase_started
  //
  // Invoked at the start of each phase. The ~phase~ argument specifies
  // the phase being started. Any threads spawned in this callback are
  // not affected when the phase ends.

  extern virtual function void phase_started (uvm_phase phase);

  // Function: phase_ready_to_end
  //
  // Invoked when all objections to ending the given ~phase~ have been
  // dropped, thus indicating that ~phase~ is ready to end. All this
  // component's processes forked for the given phase will be killed
  // upon return from this method. Components needing to consume delta
  // cycles or advance time to perform a clean exit from the phase
  // may raise the phase's objection. 
  //
  // |phase.raise_objection(this,"Reason");
  //
  // This effectively resets the
  // wait-for-all-objections-dropped loop for ~phase~. It is the
  // responsibility of this component to drop the objection once
  // it is ready for this phase to end (and processes killed).
  
  extern virtual function void phase_ready_to_end (uvm_phase phase);

  // Function: phase_ended
  //
  // Invoked at the end of each phase. The ~phase~ argument specifies
  // the phase that is ending.  Any threads spawned in this callback are
  // not affected when the phase ends.
  
  extern virtual function void phase_ended (uvm_phase phase);

読んでもよくわかりません。

で、UVM Run-Time Phases Primer内の例題でこれら関数を使っています。

この例題で使い方がわかりました。でも、超面倒です。

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