はじめに

Bluespec SystemVerilogの例題の中を調べてみるシリーズの(その1)

例題

smoke_test という例題の中を調べます。

FibOne.bsv のコードは、下記のような感じになっています。

(* synthesize *)
module mkFibOne();
   // register containing the current Fibonacci value
   Reg#(int) this_fib();              // interface instantiation
   mkReg#(0) this_fib_inst(this_fib); // module instantiation
   // register containing the next Fibonacci value
   Reg#(int) next_fib();
   mkReg#(1) next_fib_inst(next_fib);

   rule fib;  // predicate condition always true, so omitted
      this_fib <= next_fib;
      next_fib <= this_fib + next_fib;  // note that this uses stale this_fib
      $display("%0d", this_fib);
      if ( this_fib > 10000 ) $finish(0) ;
  endrule: fib
endmodule: mkFibOne

このコードを使います。

Makefileの中身

LABNAME = Smoke Test to check Bluespec installation
SMOKENAME = FibOne

BSC=bsc -no-show-timestamps -no-show-version


## Default simulator is iverilog
VSIM = -vsim iverilog

ifdef cvc
     VSIM = -vsim cvc
endif

ifdef vcs
    VSIM = -vsim vcs
endif

ifdef vcsi
    VSIM = -vsim vcsi
endif

ifdef ncverilog
    VSIM = -vsim ncverilog
endif

ifdef ncsim
    VSIM = -vsim ncsim
endif

ifdef modelsim
    VSIM = -vsim modelsim
endif

.PHONY: help
help:
    @echo "Smoke test to check Bluespec installation"
    @echo "  This tests that BSC can be run, to compile a basic design into"
    @echo "  both Verilog and Bluesim simulations, that run and produce the"
    @echo "  expected output."
    @echo
    @echo "  The default Verilog simulator is iverilog. To specity an alternate"
    @echo "  simulator, add one of the following to the comannad line:"
    @echo "    cvc=1, vcs=1, vcsi=1, ncverilog=1, ncsim=1, modelsim=1"
    @echo
    @echo "Useful targets:"
    @echo "  smoke_test         -- Run both 'smoke_test_vlog' and 'smoke_test_bsim'"
    @echo
    @echo "  smoke_test_verilog -- Run the basic test in Verilog simulation"
    @echo "  smoke_test_bluesim -- Run the basic test in Bluesim simulation"
    @echo
    @echo "  clean              --  remove intermediate files"
    @echo "  help               --  display this message"


.PRECIOUS: mk%.v

.PHONY: clean
clean:
    @rm -f *.bi *.bo *.ba 
    @rm -f *.cxx *.h *.o *.so *.bexe
    @rm -f *.v *.vexe
    @rm -f *.vcd *~ *.fsdb *.log
    @rm -f smoke_test_verilog.out smoke_test_bluesim.out
    @rm -rf csrc INCA_libs simv.daidir vfastLog/  nWaveLog/ work_mkFibOne/

## A target to check the installation of bsc
.PHONY: smoke_test
smoke_test: smoke_test_verilog smoke_test_bluesim

.PHONY: smoke_test_verilog
smoke_test_verilog: clean
    @echo ""
    @echo "Checking Verilog generation"
    $(BSC) -verilog $(SMOKENAME).bsv
    @echo ""
    @echo "Checking Verilog simulation"
    $(BSC) $(VSIM) -e mk$(SMOKENAME) -o mk$(SMOKENAME).vexe mk$(SMOKENAME).v
    ./mk$(SMOKENAME).vexe  > smoke_test_verilog.out
    @echo ""
    @echo "Comparing result of Bluespec Simulation" 
    @echo "Some simulator specific difference expected" 
    -diff mk$(SMOKENAME).out.expected smoke_test_verilog.out
    @echo ""
    @echo "Bluespec installation looks OK"

.PHONY: smoke_test_bluesim
smoke_test_bluesim: clean
    @echo ""
    @echo "Checking bsc compiles"
    $(BSC) -sim $(SMOKENAME).bsv
    @echo ""
    @echo "Checking compile for Bluespec simulator" 
    $(BSC) -sim -o mk$(SMOKENAME).bexe -e mk$(SMOKENAME) mk$(SMOKENAME).ba
    ./mk$(SMOKENAME).bexe > smoke_test_bluesim.out
    @echo ""
    @echo "Comparing result of Bluespec Simulation" 
    diff mk$(SMOKENAME).out.expected smoke_test_bluesim.out
    @echo ""
    @echo "Bluespec's Bluesim looks OK"

smoke_test_bluesim : Bluespec Simulator
smoke_test_verilog : Verilog HDL Simulator

の2つのターゲットがあるようです。

Bluespec Simulator を実行

make smoke_test_bluesim

Checking bsc compiles
bsc -no-show-timestamps -no-show-version -sim FibOne.bsv
Elaborated module file created: mkFibOne.ba

Checking compile for Bluespec simulator
bsc -no-show-timestamps -no-show-version -sim -o mkFibOne.bexe -e mkFibOne mkFibOne.ba
Bluesim object created: mkFibOne.{h,o}
Bluesim object created: model_mkFibOne.{h,o}
Simulation shared library created: mkFibOne.bexe.so
Simulation executable created: mkFibOne.bexe
./mkFibOne.bexe > smoke_test_bluesim.out

Comparing result of Bluespec Simulation
diff mkFibOne.out.expected smoke_test_bluesim.out

Bluespec's Bluesim looks OK

生成されたファイルを確認します。

ls
FibOne.bo   mkFibOne.ba       mkFibOne.cxx  mkFibOne.out.expected  model_mkFibOne.o
FibOne.bsv  mkFibOne.bexe     mkFibOne.h    model_mkFibOne.cxx     smoke_test_bluesim.out
Makefile    mkFibOne.bexe.so  mkFibOne.o    model_mkFibOne.h

下記が生成されたファイルで、

FibOne.bo
mkFibOne.ba
mkFibOne.cxx
mkFibOne.bexe
mkFibOne.h
mkFibOne.bexe.so
mkFibOne.o
model_mkFibOne.o
model_mkFibOne.cxx
model_mkFibOne.h
smoke_test_bluesim.out

bscコマンドを実行してみたら、下記のようなファイルが生成されました。

bsc -no-show-timestamps -no-show-version -sim FibOne.bsv

FibOne.bo
mkFibOne.ba

2番目のbscコマンドを実行したら、mkFibOne.ba から下記のようなファイルが生成されました。

bsc -no-show-timestamps -no-show-version -sim -o mkFibOne.bexe -e mkFibOne mkFibOne.ba

mkFibOne.cxx
mkFibOne.bexe
mkFibOne.h
mkFibOne.bexe.so
mkFibOne.o
model_mkFibOne.o
model_mkFibOne.cxx
model_mkFibOne.h

最後はプログラムを実行

./mkFibOne.bexe > smoke_test_bluesim.out

smoke_test_bluesim.out

が生成され、mkFibOne.out.expected と diff コマンドで比較しています。

mkFibOne.bexe

mkFibOne.bexe は、シェルスクリプトです。中でbluetcl を実行しています。

#!/bin/sh

BLUESPECDIR=`echo 'puts $env(BLUESPECDIR)' | bluetcl`

for arg in $@
do
  if (test "$arg" = "-h")
  then
    exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkFibOne --script_name `basename $0` -h
  fi
done
exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkFibOne --script_name `basename $0` "$@"

mkFibOne.bexe を -h オプションで実行してみる。

./mkFibOne.bexe -h
Usage: mkFibOne.bexe [opts]

Options:
  -c <commands> = execute commands given as an argument
  -f <file>     = execute script from file
  -h            = print help and exit
  -m <N>        = execute for N cycles
  -v            = print version information and exit
  -V [<file>]   = dump waveforms to VCD file (default: dump.vcd)
  +<arg>        = Verilog-style plus-arg

Examples:
  mkFibOne.bexe
  mkFibOne.bexe -c 'sim step 40; puts [sim time]'
  mkFibOne.bexe -f sim_cmds.tcl
  mkFibOne.bexe -m 3000
  mkFibOne.bexe -V sim.vcd
  mkFibOne.bexe +doFoo

mkFibOne.bexe : 最後まで実行する
mkFibOne.bexe -c 'sim step 40; puts [sim time]' : -c オプションでコマンドを指定する。コマンドは、''で囲む
mkFibOne.bexe -f sim_cmds.tcl : コマンドをファイルにストアして、-f オプションでそのファイルを指定する
mkFibOne.bexe -m 3000 : -m オプションにて実行するサイクルを指定する
mkFibOne.bexe -V sim.vcd : -V オプションで VCD dump するファイルを指定する
mkFibOne.bexe +doFoo : Verilog HDLスタイルの +オプション

おわりに

次回は、smoke_test_verilog ターゲットの部分を見てみます。

Vengineerの妄想

人生を妄想しています。

Bluespec SystemVerilog の例題の中を調べる(その1)

はじめに

例題

Bluespec Simulator を実行

mkFibOne.bexe

おわりに