はじめに
Bluespec SystemVerilogで実装されている回路例の紹介、今回はBluespecのAHB-Liteです。
TCM_AHBL_Adapter
が実態です。
パラメータとして、2ビットのverbosity があります。
module mkTCM_AHBL_Adapter #( parameter Bit #(2) verbosity // Verbosity: 0=quiet, 1 = rule firings `ifdef STANDALONE ) (TCM_AHBL_Adapter_IFC); `else , FIFOF #(Single_Req) f_single_reqs `ifdef NM32 , FIFOF #(Bit #(32)) f_single_write_data `else , FIFOF #(Bit #(64)) f_single_write_data `endif , FIFOF #(Read_Data) f_single_read_data) (TCM_AHBL_Adapter_IFC); `endif
テストベンチは、
- Testbench.bsv の mkTestbench_AXI4 です。
です。
Bit #(2) verbosity_ahbl = 2; TCM_AHBL_Adapter_IFC ahbl_adapter<- mkTCM_AHBL_Adapter ( verbosity_ahbl); AHBL_Target_AXI4_Initiator xactor <- mkAHBL_Target_AXI4_Initiator; mkConnection (ahbl_adapter.mem_master, xactor.ahbl_target);
mkTCM_AHBL_Adapterのパラメータであるverbosity_ahbl に 2 を設定しています。2だと、reset の時のメッセージも表示するようです。
mkAHBL_TargetAXI4_Initiator は、ここで定義されています。
このトップテストベンチ mkTestbench_AXI4 は、AHB-Lite/build/AHBL-AXI4-RV32-Fabric32/Makefile で使われています。
ビルドディレクトリにて、compile ターゲットを実行すると、Semi_FIFOF と EdgeFIFOs が無いと怒られます。Semi_FIFOFと EdgeFIFOs は RISC-V CPU の Flute の中(src_Core/BSV_Additional_Libs/Semi_FIFOF.bsv)にあるので、これをとりあえず、src にコピーします。
再度、make を実行すると、なんだか、rule が conflict していると怒られます。。。なんで？
cd build/AHBL-AXI4-RV32-Fabric32
export PATH=BSC_bin:${PATH}
make compile
INFO: Verilog RTL generation ...
bsc -u -elab -sim -bdir build_dir -simdir build_dir -info-dir build_dir -D RV32 -D FABRIC32 -D STANDALONE -keep-fires -aggressive-conditions -no-warn-action-shadowing -no-show-timestamps -check-assert -suppress-warnings G0020 +RTS -K128M -RTS -show-range-conflict -p ../../src:../../src_tb:../../BSV_Additional_Libs:+ ../../src_tb/Testbench.bsv
Warning: Command line: (S0091)
Removing a directory from the path specified with the -p flag, because it
could not be opened.
Directory:
../../BSV_Additional_Libs
System message:
does not exist
checking package dependencies
compiling ../../src/AHBL_Types.bsv
compiling ../../src/AHBL_Defs.bsv
compiling ../../src/EdgeFIFOFs.bsv
compiling ../../src/Semi_FIFOF.bsv
compiling ../../src_tb/AXI4_Types.bsv
compiling ../../src_tb/Testbench_Commons.bsv
compiling ../../src/TCM_AHBL_Adapter.bsv
code generation for mkTCM_AHBL_Adapter starts
Elaborated module file created: build_dir/mkTCM_AHBL_Adapter.ba
compiling ../../src_tb/AHBL_Target_AXI4_Initiator.bsv
code generation for mkAHBL_Target_AXI4_Initiator starts
Warning: "../../src_tb/AHBL_Target_AXI4_Initiator.bsv", line 61, column 8: (G0010)
Rule "rl_ahbl_new_req" was treated as more urgent than
"rl_write_rsp". Conflicts:
"rl_ahbl_new_req" cannot fire before "rl_write_rsp":
calls to rg_wr_rsps_pending.write vs. rg_wr_rsps_pending.read
"rl_write_rsp" cannot fire before "rl_ahbl_new_req":
calls to rg_wr_rsps_pending.write vs. rg_wr_rsps_pending.read
Elaborated module file created: build_dir/mkAHBL_Target_AXI4_Initiator.ba
compiling ../../src_tb/Testbench.bsv
code generation for mkTestbench_AXI4 starts
Warning: "../../src_tb/Testbench.bsv", line 118, column 8: (G0010)
Rule "rl_init_mem" was treated as more urgent than "rl_wr_req". Conflicts:
"rl_init_mem" cannot fire before "rl_wr_req":
calls to rg_state.write vs. rg_state.read
"rl_wr_req" cannot fire before "rl_init_mem":
calls to rg_state.write vs. rg_state.read
Warning: Unknown position: (S0080)
1 warnings were suppressed.
Error: "../../src_tb/Testbench.bsv", line 131, column 31: (G0066)
Instance `xactor' requires the following method to be always enabled, but
the condition for executing the method is always False:
ahbl_target_hready
This can be because the method is not used in any rules or because the
condition of those uses can be shown to be False.
make: *** [Makefile:51: compile] Error 1
おわりに
わからないのですが、とりあえず、ここに残しておきます。
