SpinalHDLのRISC-V

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SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

SpinalHDLという言語で実装したRISC-VベースのSoC

RISC-VベースなSoCのドキュメントは、ここ、回路の説明はここ

で、SpinalHDLとは？

引用
 Spinal is a open source high-level hardware description language. 
 It can be used as an alternative to VHDL or Verilog 
 and has several advantages over those.

 Also Spinal is not a HLS approch, 
 its goal is not to push something abstract into flip-flop and gates, 
 but by using simple elements (flip-flop, gates, if / case statments) 
 create new abstraction level 
 and help the designer to not rewrite always the same thing.

 Note: Spinal is fully interoperable with standard VHDL/Verilog-based EDA tools 
       (simulators and synthetizers) as the output generated by the toolchain 
       could be VHDL or Verilog. 

       It also enables mixed designs where Spinal components inter-operate 
       with VHDL or Verilog IPs.

どんどん作っているね。