はじめに
Huawei Ascend 910Cの詳細について、Xの投稿に流れてきましたので、記録に残します。
🚨 Brand new details on Huawei’s Ascend 910C chip and CloudMatrix384 system!
— Jacob Feldgoise (@jacob_feldgoise) 2025年6月17日
A new paper from Huawei confirms what we suspected about the architecture, throughput, and HBM of the Ascend 910C NPU.
More details: 🧵 pic.twitter.com/lP3cTIYPf7
Hauwei Ascend 910 の振り返り
- HuaweiのDa Vince (Ascend 910/310)
- Huawei Ascend 910シリーズ
- Huawei Ascend 910C の歩留まりが向上！
- Huawei Ascend 910C って、2 die なんだ！
NotebookLMの音声概要
論文
下記の上記の論文から説明のために引用します。
At the core of CloudMatrix 384 is the HiSilicon Ascend 910C NPU, Huawei’s 2024-era flagship AI accelerator that succeeds the original Ascend 910B. The 910C is a dual-die package: two identical compute dies are co-packaged, sharing eight on-package memory stacks and connected by a high-bandwidth cross-die fabric, as shown in Figure 3.
Compute. Each die contains 24 AI cube (AIC) cores, optimized for matrix and convolution workloads, and 48 AI vector (AIV) cores for element-wise operations. All compute engines support FP16/BF16 and INT8 data types. The 8-bit quantization can be implemented with INT8 precision, enabling computational efficiency comparable to native FP8 hardware without requiring dedicated FP8 support. The two dies communicate over an on-package interconnect that provides up to 540 GB/s of total bandwidth, 270 GB/s per direction.
Memory. The Ascend 910C package integrates eight memory stacks (16 GB each), providing a total of 128 GB of on-package memory (64 GB per die). The package delivers up to 3.2 TB/s of aggregate memory bandwidth, with 1.6 TB/s available per die.
Network Interfaces. Each Ascend 910C die interfaces with two distinct network planes.
- 1) UB Plane: The die integrates seven high-speed transceivers, each operating at 224 Gbps, providing a total of 196 GB/s unidirectional (or 392 GB/s bidirectional) bandwidth to the scale-up UB plane.
- 2) RDMA Plane: Separately, each die includes a dedicated interface delivering up to 200 Gbps of unidirectional bandwidth for the scale-out RDMA plane.
Network Interface の部分ですが、上記のブログでも引用している Die shot をここでも説明のために引用します。
Die の右側に、
- Huawei Cache Coherent System
- PCIe x4 が4組
あります。
- UB Plane <=> Huawei Cache Coherent System
- RDMA Plane <=> PCIe x4 が4組 (200Gbps なので、PCIe Gen4@16Gbps x 4 x 4 16 x 16 = 256Gbps で 200 Gbps の Ethernet の接続可能)
おわりに
Huawei Ascend 910 は、TSMC 7nm で実装され、2019年に発表されています。当時は、NVIDIAのA100ベースのシステムと同等かそれ以上のものだった気がします。
