Verification Engineerの戯言
アジェンダは、つぎのようになっています。
引用:
引用:
* Introduction * OVM Methodology and Overview * OVM-SC library overview * OVM_SC object and component base classes * Phased test flow * Top-down parameter configuration and type overrides of the design components * Connecting HDL DUT to SystemC test environment * Demonstration * OVM-SC Free Package Description & Access * Question and Answer Session
検証、Verification、SystemVerilog、OVM、Open Verification Methodology、SystemC