IEEE 1800-2012を知りたい

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SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

DVCon2012での論文：
Keeping Up with Chip ― the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficientを読むと、
SystemVerilog-2012のことがちょこっと知ることができます。

いろんな機能が追加されているんですが、多重継承というのもあります。

引用
　　3. Multiple inheritance (Mantis 1356)

　　This new feature is one of the most significant efficiency enhancements 
    in the proposed SystemVerilog-2012 standard. 
    Multiple inheritance allows a child class to inherit properties 
    and methods from more than one parent class. The proposed SystemVerilog-2012 uses
    Java-like interface classes to do multiple inheritance.

    In brief, a SystemVerilog interface class can define:

        • Parameter constants
        • User-defined types (typedefs)
        • Pure virtual method prototypes

    A regular class can then implement one or more interface classes. 
    The full syntax, semantic rules and mechanics of interface classes 
    is beyond the scope of this paper. A simple usage of interface classes 
    and multiple inheritance is illustrated in the following example 
    (bold text shows the important new features):

    interface class Put;
        pure virtual function void put(int a);
    endclass

    interface class Get;
        pure virtual function int get();
    endclass

    //inherit method prototypes from multiple parents
    class Fifo implements Put, Get;
        ... // implementations of inherited methods
    endclass

ですが、ほんとうにJavaみたいですね。

ますます複雑になるのって、ほんとうにいいのでしょうかね？

検証、Verification、SystemVerilog