The UVM Primer

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SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

The UVM Primerのビデオ。
何故か？ Chapter4と14がありません。4を嫌ったのでしょうか？

    Chapter 1: Introduction and Device Under Test
    Chapter 2: Conventional Testbench for the TinyALU
    Chapter 3: SystemVerilog Interfaces and Bus Functional Models

    Chapter 5: Classes and Extension
    Chapter 6: Polymorphism
    Chapter 7: Static Methods and Variables
    Chapter 8: Parameterized Class Definitions
    Chapter 9: The Factory Pattern
    Chapter 10: An Object-Oriented Testbench
    Chapter 11: UVM Tests
    Chapter 12: UVM Components
    Chapter 13: UVM Environments

    Chapter 15 Talking to Multiple Objects
    Chapter 16: Using Analysis Ports in the Testbench
    Chapter 17: Interthread Communication
    Chapter 18: Put and Get Ports in Action
    Chapter 19: UVM Reporting
    Chapter 20: Class Hierarchies and Deep Operations
    Chapter 21: UVM Transactions Part 2
    Chapter 22: UVM Agents
    Chapter 23: UVM Sequences

検証、Verification、SystemVerilog、UVM