2018/11/15(木)にこのブログに書いたBitmainのチップが載った 96Boards
その続きがなかなか出てこなかったけど、出てきてた。。。
このブログの中に書いてあるLinuxへのパッチ：[PATCH 0/5 Add initial Bitmain BM1880 SoC/Board support]
引用 Hello, This patchset adds initial support for Bitmain BM1880 SoC and Sophon Edge board. BM1880 SoC consists of a Dual Core ARM Cortex A53 Application processor subsystem, a single core RISC-V subsystem and a Tensor Processor subsystem. This patchset adds support for only ARM Cortex A53 Application processor subsystem with UART, which enables the board to boot into initramfs with 2 CPUs. Thanks, Mani Manivannan Sadhasivam (5): dt-bindings: arm: Document Bitmain BM1880 SoC arm64: Add ARCH_BITMAIN platform arm64: dts: bitmain: Add BM1880 SoC support arm64: dts: bitmain: Add Sophon Egde board support MAINTAINERS: Add entry for Bitmain SoC platform .../devicetree/bindings/arm/bitmain.yaml | 18 +++ MAINTAINERS | 7 ++ arch/arm64/Kconfig.platforms | 5 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bitmain/Makefile | 3 + .../boot/dts/bitmain/bm1880-sophon-edge.dts | 50 ++++++++ arch/arm64/boot/dts/bitmain/bm1880.dtsi | 119 ++++++++++++++++++ 7 files changed, 203 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bitmain.yaml create mode 100644 arch/arm64/boot/dts/bitmain/Makefile create mode 100644 arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts create mode 100644 arch/arm64/boot/dts/bitmain/bm1880.dtsi
内容的には、dtsファイルを追加した感じ。
で、arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi は、下記のように、
Cortex-A53が2コア。
メモリは1GBなんですが、予約領域として
Cortex-A53が2コア。
メモリは1GBなんですが、予約領域として
・secmon用として、32KB ・JPU用として、128MB ・VPU用として、128MBを使っているので、CPUコアが使えるメモリ量って、768MBぐらいなんですね。
UARTが4チャネル。。。
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Linaro Ltd. + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "bitmain,bm1880"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secmon@100000000 { + reg = <0x1 0x00000000 0x0 0x20000>; + no-map; + }; + + jpu@130000000 { + reg = <0x1 0x30000000 0x0 0x08000000>; // 128M + no-map; + }; + + vpu@138000000 { + reg = <0x1 0x38000000 0x0 0x08000000>; // 128M + no-map; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@50001000 { + compatible = "arm,gic-400"; + reg = <0x0 0x50001000 0x0 0x1000>, + <0x0 0x50002000 0x0 0x2000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@5801A000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x5801a000 0x0 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@5801C000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x5801c000 0x0 0x2000>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@5801E000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x5801e000 0x0 0x2000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + }; +};
