SV/UVM based instruction generator for RISC-V processor verification

@Vengineerの戯言 : Twitter
SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった 

見つけた。

github.com

ただし、お高いシミュレータが必要。

To be able to run the instruction generator, you need to have an RTL simulator which supports SystemVerilog and UVM 1.2. This generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, and Mentor Questa simulators. Please make sure the EDA tool environment is properly setup before running the generator.

 あら、

Co-simulation with multiple ISS : spike, riscv-ovpsim, whisper, sail-riscv

 とあるけど。。。

テストは、アセンブラだけでなく、Cでもできる模様。