D => PLI Wrapper => CのPLI => Verilog HDL Simulatorで、繋がるようです。
UVMも利用出来るということ。
下記にあるように、Verilog HDL だけでなく、VHDLやSystemCでもOKになるようです。
引用
Compatibility with other Languages
Vlang is highly compatible with other languages commonly used in simulation
and verification process.
・C/C++/SystemC: D is ABI compatible with C/C++.
By the virtue of this Vlang is interoperable with C/C++/SystemC
and Vlang with C/C++/SystemC will create one single executable after linking.
・Verilog/SystemVerilog: Vlang implements VPI interface of Verilog Standard
and hence Verilog models can be integrated seamlessly with Vlang.
・VHDL: Vlang implements VHPI interface of VHDL Standard
and hence VHDL models can be integrated seamlessly with Vlang.
・MATLAB: Golden models written in MATLAB can be seamlessly integrated
with Vlang through matlab-mex interfaces.
いかがでしょうか?